US-20260128978-A1 - GENERATING NETWORK DEFINITIONS FROM HIERARCHICAL TOPOLOGY OF CONTROL AND STATUS REGISTERS

Abstract

System and method for generating a Network on Chip (NoC) includes intaking a specification, where the specification includes, for each sub-NoC design, hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations thereof. Further, for each of the CSR controller in the sub-NoC, the sub-NoC design includes a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers and ingress and egress points of a boundary of the each sub-NoC. The network definition is generated for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points. NoCs may be generated based on the network definitions.

Inventors

• Honnahuggi Harinath Venkata Naga Ambica Prasad
• Narayana Sri Harsha Gade
• Eric Norige

Assignees

• Baya Systems, Inc.

Dates

Publication Date

20260507

Application Date

20250107

Priority Date

20241105

Claims (18)

1. 1 . A method for generating a Network on Chip (NoC) system, the method comprising: intaking a specification comprising, for each sub-NoC design: hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations; for each of the CSR controllers in the sub-NoC, a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers; and ingress and egress points of a boundary of the each sub-NoC; generating a CSR network definition for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a CSR routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points; and generating a NoC based on the CSR network definitions.
2. 2 . The method of claim 1 , wherein the specification further comprises controller access points, and a mapping of the set of CSR endpoints and the controller access points to the CSR controllers of the NoC, and wherein the mapping is generated for the specification.
3. 3 . The method of claim 1 , wherein the computation of routes further comprises computing routes between the set of CSR endpoints and controller access points to the CSR controllers of the NoC.
4. 4 . The method of claim 1 , further comprising transforming the set of CSR endpoints to component association in the CSR network definition based on optimization of one or more of: wire cost, address space, area cost, or number of registers.
5. 5 . The method of claim 1 , wherein the CSR routing graph is reweighted and trimmed based on the ingress and egress points.
6. 6 . The method of claim 1 , wherein the set of CSR endpoints comprise endpoints outside of the each sub-NoC design.
7. 7 . A computer-readable storage medium storing instructions for executing a process, comprising: intaking a specification comprising, for each sub-NoC design: hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations; for each of the CSR controllers in the sub-NoC, a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers; and ingress and egress points of a boundary of the each sub-NoC; generating a CSR network definition for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a CSR routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points; and generating a NoC based on the CSR network definitions.
8. 8 . The computer-readable storage medium of claim 7 , wherein the specification further comprises controller access points, and a mapping of the set of CSR endpoints and the controller access points to the CSR controllers of the NoC, and wherein the mapping is generated for the specification.
9. 9 . The computer-readable storage medium of claim 7 , wherein the computation of routes further comprises computing routes between the set of CSR endpoints and controller access points to the CSR controllers of the NoC.
10. 10 . The computer-readable storage medium of claim 7 , further comprising transforming the set of CSR endpoints to component association in the CSR network definition based on optimization of one or more of: wire cost, address space, area cost, or number of registers.
11. 11 . The computer-readable storage medium of claim 7 , wherein the CSR routing graph is reweighted and trimmed based on the ingress and egress points.
12. 12 . The computer-readable storage medium of claim 7 , wherein the set of CSR endpoints comprise endpoints outside of the each sub-NoC design.
13. 13 . A system, comprising a control module configured to: intake a specification comprising, for each sub-NoC design: hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations; for each of the CSR controllers in the sub-NoC, a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers; and ingress and egress points of a boundary of the each sub-NoC; generate a CSR network definition for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a CSR routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points; and generate a NoC based on the CSR network definitions.
14. 14 . The system of claim 13 , wherein the specification further comprises controller access points, and a mapping of the set of CSR endpoints and the controller access points to the CSR controllers of the NoC, and wherein the mapping is generated for the specification.
15. 15 . The system of claim 13 , wherein the computation of routes further comprises computing routes between the set of CSR endpoints and controller access points to the CSR controllers of the NoC.
16. 16 . The system of claim 13 , further comprising transforming the set of CSR endpoints to component association in the CSR network definition based on optimization of one or more of: wire cost, address space, area cost, or number of registers.
17. 17 . The system of claim 13 , wherein the CSR routing graph is reweighted and trimmed based on the ingress and egress points.
18. 18 . The system of claim 13 , wherein the set of CSR endpoints comprise endpoints outside of the each sub-NoC design.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to IN 202411084721, filed on Nov. 5, 2024, the contents of which are incorporated herein by reference. BACKGROUND Technical Field Methods and example embodiments described herein are generally directed to designing registers for components of Network on Chips (NoCs), and more specifically, to automatic generation of control and status registers (CSRs) based on component configurations of the NoC. Related Art The number of components on a chip is rapidly growing due to increasing levels of integration, system complexity, and shrinking transistor geometry. Complex System-on-Chips (SoCs) may involve a variety of components, e.g., processor cores, digital signal processors (DSPs), hardware accelerators, memory, and Input/Output (I/O) subsystems, while Chip Multi-Processors (CMPs) may involve a large number of homogenous processor cores, memory, and I/O subsystems. In both systems, the on-chip interconnect plays a key role in providing high-performance communication between the various components. Due to scalability limitations of traditional buses and crossbar-based interconnects, Network-on-Chip (NoC) has emerged as a paradigm to interconnect a large number of components on the chip. NoC is a global shared communication infrastructure made up of several routing nodes interconnected with each other using point-to-point physical links. Messages are injected by the source and are routed from the source node/router to the destination node/router over multiple intermediate nodes and physical links. The destination node/router then ejects the message and provides it to the destination. For the remainder of the document, terms ‘processing elements,’ ‘components,’ ‘blocks,’ ‘hosts,’ or ‘cores,’ will be used interchangeably to refer to the various system components which are interconnected using a NoC. Further, terms ‘routers’ and ‘nodes’ may also be used interchangeably. Without loss of generalization, the system with multiple interconnected components will itself be referred to as a ‘multi-core system.’ There are several possible topologies in which the routers can connect to one another to create the system network. Bi-directional rings 100A (as shown in FIG. 1A) and 2-D mesh 100B (as shown in FIG. 1B) are examples of topologies in the related art. Packets are message transport units for intercommunication between various components. Routing involves identifying a path which is a set of routers and physical links of the network over which packets are sent from a source to a destination. Components are connected to one or multiple ports of one or multiple routers, with each such port having a unique identifier (ID). Packets carry the destination's router and port ID for use by the intermediate routers to route the packet to the destination component. Examples of routing techniques include deterministic routing, which involves choosing the same path from A to B for every packet. This form of routing is oblivious to the state of the network and does not load balance across path diversities which may exist in the underlying network. However, such deterministic routing may be simple to implement in hardware, maintains packet ordering, and may be easy to make free of network-level deadlocks. Shortest path routing minimizes the latency as it reduces the number of hops from the source to the destination. For this reason, the shortest path is also the lowest power path for communication between the two components. Dimension-order routing is a form of deterministic shortest-path routing in 2D mesh networks. FIG. 2 illustrates an example of XY routing in a two-dimensional mesh 200. More specifically, FIG. 2 illustrates XY routing from node ‘34’ to node ‘00.’ In the example of FIG. 2, each component is connected to only one port of one router. A packet is first routed in the X dimension till the packet reaches node ‘04,’ where the x dimension is same as the destination. The packet is next routed in the Y dimension until the packet reaches the destination node. Source routing and routing using tables are other routing options used in NoC. Adaptive routing can dynamically change the path taken between two points in the network based on the state of the network. This form of routing may be complex to analyze and implement and is therefore rarely used in practice. A NoC may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, where different message types are transmitted over different virtual networks. In this case, at each physical link or channel, there are multiple virtual channels, where each virtual channel may have dedicated buffers at both end points. In any given clock cycle, only one virtual channel can transmit data on the physical channel. NoC interconnects often employ wormhole routing, where a large message or packet is broken into small pieces known as flits (also referred to as flow control