US-20260129321-A1 - SYSTEMS AND METHODS FOR SWITCHING

Abstract

Systems and methods for switching are disclosed. In an example, a switching system includes a photonic integrated circuit (PIC) having optical ports, an electric integrated circuit (EIC) stacked on the PIC and having switching circuitry, and photonic transceivers optically coupled to the optical ports of the PIC and electrically coupled to the switching circuitry of the EIC, and the switching circuitry is configured to transfer digital signals, which are generated from optical signals received at a first photonic transceiver of the photonic transceivers, to a second photonic transceiver of the photonic transceivers based on information in the digital signals, wherein the first photonic transceiver is optically coupled to a first optical port of the PIC and the second photonic transceiver is optically coupled to a second optical port of the PIC.

Inventors

• David Lazovsky
• Philip Winterbottom
• Francisco Jose Maia Da Silva
• Martinus Bos

Assignees

• CELESTIAL AI INC.

Dates

Publication Date

20260507

Application Date

20251218

Claims (17)

1. 1 . An integrated circuit device comprising: switching circuitry; and a plurality of first portions of photonic transceivers, each first portion of a photonic transceiver including a driver and a driver interface that is exposed at a major surface of the integrated circuit device and an amplifier and an amplifier interface that is exposed at the major surface of the integrated circuit device; wherein the switching circuitry is configured to transfer digital signals, which are generated from electrical signals received from the first portion of a first photonic transceiver, to the first portion of a second photonic transceiver based on information in the digital signals.
2. 2 . The integrated circuit device of claim 1 , wherein the major surface of the integrated circuit device is bottom major surface of the integrated circuit device.
3. 3 . The integrated circuit device of claim 1 , wherein: the major surface of the integrated circuit device is a bottom major surface of the integrated circuit device; the driver interface of each photonic transceiver is located on the bottom major surface of the integrated circuit device to align with a modulator interface on a photonic integrated circuit (PIC); and the amplifier interface of each photonic transceiver is located on the bottom major surface of the integrated circuit device to align with a photodetector interface on the PIC.
4. 4 . The integrated circuit device of claim 1 , wherein: the driver interface of each photonic transceiver is located on the integrated circuit device to align with a modulator interface on a photonic integrated circuit (PIC); and the amplifier interface of each photonic transceiver is located on the integrated circuit device to align with a photodetector interface on the PIC.
5. 5 . The integrated circuit device of claim 1 , wherein the switching circuitry includes a switch fabric.
6. 6 . The integrated circuit device of claim 1 , wherein the switch fabric is a crosspoint matrix.
7. 7 . The integrated circuit device of claim 1 , wherein the switching circuitry is configured to identify a photonic transceiver of the integrated circuit device to transfer digital signals to based on information in a media access control (MAC) table that is stored in the integrated circuit device.
8. 8 . The integrated circuit device of claim 1 , wherein a first set of the plurality of first portions of photonic transceivers surrounds a second set of the plurality of first portions of photonic transceivers.
9. 9 . The switching system of claim 1 , wherein the integrated circuit device has a footprint, and wherein the first portions of the photonic transceivers are located in an interior region of the footprint of the integrated circuit device.
10. 10 . The integrated circuit device of claim 1 , wherein a first set of the plurality of first portions of photonic transceivers corresponds to spine photonic transceivers and a second set of the plurality of first portions of photonic transceivers corresponds to leaf photonic transceivers.
11. 11 . The integrated circuit device of claim 1 , wherein a first set of the plurality of first portions of photonic transceivers corresponds to spine photonic transceivers and a second set of the plurality of first portions of photonic transceivers corresponds to leaf photonic transceivers, wherein the switching circuitry surrounds the spine photonic transceivers and the leaf photonic transceivers surround the switching circuitry.
12. 12 . A method comprising: amplifying analog electrical signals that are received at an amplifier interface of a first portion of a first photonic transceiver of an integrated circuit device, wherein the amplifier interface is exposed at a major surface of the integrated circuit device and electrically coupled to an amplifier of the first photonic transceiver; converting the amplified analog electrical signals to digital signals within the integrated circuit device; transferring the digital signals to a second photonic transceiver of the integrated circuit device via switching circuitry of the integrated circuit device based on information in the digital signals; and driving a driver of the second photonic transceiver in response to the digital signals to generate analog electrical signals at a driver interface of a first portion of the second photonic transceiver, wherein the driver interface is exposed at the major surface of the integrated circuit device.
13. 13 . The method of claim 12 , wherein transferring the digital signals to the second photonic transceiver of the integrated circuit device via the switching circuitry based on information in the digital signals involves identifying an output optical port based on a media access control (MAC) table in the switching circuitry.
14. 14 . The method of claim 12 , wherein the EIC includes spine photonic transceivers and leaf photonic transceivers, and wherein the first photonic transceiver is a leaf photonic transceiver and the second photonic transceiver is a spine photonic transceiver.
15. 15 . The method of claim 12 , wherein the EIC includes spine photonic transceivers and leaf photonic transceivers, and wherein the first photonic transceiver is a spine photonic transceiver and the second photonic transceiver is a leaf photonic transceiver.
16. 16 . The method of claim 12 , wherein the EIC includes interior photonic transceivers surrounded by exterior photonic transceivers, and wherein the first photonic transceiver is an exterior photonic transceiver and the second photonic transceiver is an interior photonic transceiver.
17. 17 . The method of claim 12 , wherein the EIC includes interior photonic transceivers surrounded by exterior photonic transceivers, and wherein the first photonic transceiver is an interior photonic transceiver and the second photonic transceiver is an exterior photonic transceiver.

Description

CROSS-REFERENCES This is a U.S. continuation application under 35 U.S.C. 111(a) claiming priority under 35 U.S.C. 120 to international patent application PCT/US2024/052458, filed Oct. 22, 2024, which is incorporated by reference herein, and which is entitled to the benefit of provisional U.S. Patent Application Ser. No. 63/592,509, filed Oct. 23, 2023, also incorporated by reference herein. BACKGROUND Demands for artificial intelligence (AI) computing, such as machine learning (ML) and deep learning (DL), are increasing faster than they can be met by increases in available processing capacity. This rising demand and the growing complexity of AI models drive the need to move large volumes of data between compute and/or memory nodes in a data center. In many conventional systems, data movement leads to significant power consumption, poor performance, and excessive latency. Thus, multi-node computing systems that can process and transmit data between nodes quickly and efficiently may be advantageous for the implementation of AI computing. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a perspective view of an example of a circuit package that includes an EIC that is stacked on a PIC to produce a multiport network switch. FIG. 1B is a side view of the circuit package from FIG. 1A that includes the EIC and the PIC, and in which the PIC is mounted on a substrate. FIG. 2A is a side view of an example photonic transceiver of a multiport network switch relative to an EIC and a PIC in which a portion of the photonic transceiver is embodied in the EIC and a portion of the photonic transceiver is embodied in the PIC. FIG. 2B is an expanded side view of the photonic transceiver from FIG. 2A. FIG. 3A is a top view of an example of a multiport network switch that is coupled between four different nodes that are external to the multiport network switch. FIG. 3B is a bottom perspective view of the EIC of FIG. 3A. FIG. 3C is a side cutaway view of the multiport network switch from FIG. 3A. FIG. 4 illustrates the communication of digital data between a multiport network switch and a node. FIG. 5A is a top view of an example multiport network switch that is configured for use in a leaf-spine network architecture. FIG. 5B is a bottom perspective view of the EIC of FIG. 5A. FIG. 5C is a side cutaway view of the multiport network switch from FIGS. 5A and 5B. FIG. 6 is an example of a leaf-spine network architecture in which multiport network switches as described with reference to FIG. 5A-5C are used as switches in the leaf-spine network architecture. FIG. 7 is a top view of the multiport network switch as described with reference to FIG. 5A-5C in which the optical ports of the multiport network switch are labeled with the node or spine switch to which the optical port is optically coupled and in which the photonic transceivers are labeled with the corresponding optical port numbers to which the photonic transceivers are optically coupled. FIG. 8 is an example of the switching circuitry that may be implemented in the multiport network switch. FIG. 9 is an example of a MAC table that can be maintained and utilized by the switching circuitry. FIG. 10A is an example of a multiport network switch in which the photonic transceivers are located on opposite sides of the switching circuitry. FIG. 10B is an example of a multiport network switch in which the photonic transceivers are arranged in a mesh configuration relative to the switching circuitry. FIG. 11A is a top view of an example of a multiport network switch that is configured with a matrix of photonic transceiver cells. FIG. 11B is a bottom perspective view of the EIC of FIG. 11A. FIG. 11C is a top view of the multiport network switch as described with reference to FIGS. 11A and 11B in which the optical ports and the photonic transceivers are labeled with the corresponding optical port numbers. FIG. 12 is a process flow diagram of a method for switching network traffic, using for example, a multiport network switch as described herein. FIG. 13 is a process flow diagram of a method for switching network traffic, using for example, an integrated circuit device (e.g., an EIC) as described herein. Throughout the description, similar reference numbers may be used to identify similar elements. DETAILED DESCRIPTION A multiport network switch is used to direct network traffic from an input port of the multiport network switch to an output port of the multiport network switch based on some information in the network traffic, e.g., some header information in data packets of the network traffic. With higher levels of integration, much of the functionality of a multiport network switch can be integrated into a single chip, e.g., a single IC device. While various examples of single-chip multiport network switches exist, the data interfaces to and from the IC devices, often referred to as media independent interfaces (MIIs), are physically located at the edge, or beachfront, of the IC devices a