US-20260129500-A1 - Sixty Gigahertz Multiple Input Multiple Output Transceiver

US20260129500A1US 20260129500 A1US20260129500 A1US 20260129500A1US-20260129500-A1

Abstract

An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.

Inventors

Patrick Soon-Shiong
Vincent Dang
Zaw Soe

Assignees

TENSORCOM, LLC

Dates

Publication Date: 20260507
Application Date: 20260106

Claims (20)

1 . A system-on-chip (SoC) device for a communication system, the SoC device comprising: a first communication interface configured to receive data in the communication system; a producer port linked with a consumer port through direct memory access (DMA), wherein data received by the first interface is assigned to the producer port; dual hardware media access controls (MACs) configured to consume the data assigned to the producer port; and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz, wherein the wireless interface includes at least one beamforming chip configured to transmit wireless communication signals, wherein an aggregation layer of the SoC device is configured to synchronize the dual MACs and reassemble two independent MAC data streams into a single data stream, wherein the aggregation layer is configured to reorder out-of-order data frames using 802.11 protocol sequence numbers, committing only in-order frames to a next processing step and holding out-of-order data frames until they can be reordered or a timeout occurs, and wherein the at least one processor is configured to reduce a specified modulation rate in response to an out-of-order frame arrival rate increasing above a specified degradation threshold, and increase the specified modulation rate in response to the out-of-order frame arrival rate decreasing below the specified degradation threshold.
2 . The SoC device of claim 1 , wherein the first interface is configured to receive the data from a distributed unit of a fronthaul communication system architecture, wherein the distributed unit is in communication with a core network of the communication system.
3 . The SoC device of claim 1 , wherein the first interface is configured to receive the data from a radio unit of a fronthaul communication system architecture, wherein: the radio unit is electrically coupled with at least one cellular antenna; and the radio unit is configured to transmit and receive wireless cellular signals.
4 . The SoC device of claim 1 , wherein, the other wireless communication device includes: a second interface configured to receive data in the communication system; a second producer port linked with a second consumer port through DMA; second dual hardware media access controls configured to consume the data assigned to the producer port; and at least one second processor configured to receive, via a second wireless interface, the data transmitted at the frequency of at least sixty Gigahertz.
5 . The SoC device of claim 4 , wherein the second wireless interface includes a second beamforming chip configured to transmit wireless communication signals to the wireless interface including the first beamforming chip.
6 . The SoC device of claim 5 , further comprising at least one antenna array, wherein each beamforming chip is arranged as part of the at least one antenna array.
7 . The SoC device of claim 5 , wherein each beamforming chip is configured to apply a beamforming gain of at least 23 decibels.
8 . The SoC device of claim 5 , wherein each beamforming chip is configured to transmit wireless communication signals at a frequency of at least 60 GHz.
9 . The SoC device of claim 4 , wherein the data received by the second interface includes radio over Ethernet (RoE) data.
10 . The SoC device of claim 1 , wherein the data received by the first interface includes enhanced common public radio interface (eCPRI) data received from an eCPRI field programmable gate array (FPGA).
11 . The SoC device of claim 1 , wherein the at least one processor is configured to establish control communication channels between a backhaul field programmable gate array (FPGA) and the SoC device through dedicated peripheral component interconnect express (PCIe) ports to central processing unit (CPU) consumer ports.
12 . The SoC device of claim 1 , wherein: the at least one processor is configured to handle lower MAC processes of the SoC device; and upper MAC processes reside on an application processor of a backhaul field programmable gate array (FPGA).
13 . The SoC device of claim 12 , wherein according to a ping-pong protocol, frames of data are sent out in a round-robin manner based on which MAC is able to access the wireless interface.
14 . The SoC device of claim 12 , wherein each radio channel stream is configured to operate according to the specified modulation rate which allows each MAC to independently request MAC protocol data unit (MPDU) payload from a shared memory space.
15 . A method of operating a system-on-chip (SoC) device for a communication system, the method comprising: receiving, via a first interface, data from in a communication system; assigning data received by the first interface to a producer port linked with a consumer port through direct memory access (DMA); consuming the data assigned to the producer port via dual hardware media access controls (MACs); and supplying the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz, wherein the wireless interface includes at least one beamforming chip configured to transmit wireless communication signals, wherein an aggregation layer of the SoC device is configured to synchronize the dual MACs and reassemble two independent MAC data streams into a single data stream, wherein the aggregation layer is configured to reorder out-of-order data frames using 802.11 protocol sequence numbers, committing only in-order frames to a next processing step and holding out-of-order data frames until they can be reordered or a timeout occurs; reducing a specified modulation rate in response to an out-of-order frame arrival rate increasing above a specified degradation threshold; and increasing the specified modulation rate in response to the out-of-order frame arrival rate decreasing below the specified degradation threshold.
16 . The method of claim 15 , wherein: receiving the data includes receiving the data at the first interface from a distributed unit of a fronthaul communication system architecture; and the distributed unit is in communication with a core network of the communication system.
17 . The method of claim 15 , wherein: receiving the data includes receiving the data at the first interface from a radio unit of a fronthaul communication system architecture; the radio unit is electrically coupled with at least one cellular antenna; and the radio unit is configured to transmit and receive wireless cellular signals.
18 . The method of claim 15 , wherein, the other wireless communication device includes: a second interface configured to receive data in the communication system; a second producer port linked with a second consumer port through DMA; second dual hardware media access controls configured to consume the data assigned to the producer port; and at least one second processor configured to receive, via a second wireless interface, the data transmitted at the frequency of at least sixty Gigahertz.
19 . The method of claim 18 , wherein the second wireless interface includes a second beamforming chip configured to transmit wireless communication signals to the wireless interface including the first beamforming chip.
20 . The method of claim 15 , wherein the data received by the first interface includes radio over Ethernet (RoE) data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/982,860, field on Dec. 12, 2024, which claims the benefit and priority of U.S. Provisional Application No. 63/672,986, filed on Jul. 18, 2024. The entire disclosure of each of the above applications is herein incorporated by reference. FIELD The present disclosure relates systems and methods for sixty Gigahertz wireless communication using a multiple-input multiple-output transceiver. BACKGROUND Cellular infrastructure is evolving towards a denser network with higher capacity, necessitating the use of higher frequency bands. With the rise of 5G, open radio architecture plays a pivotal role in this transformation. Open Radio Access Networks (O-RAN) allow for more flexible, cost-effective, and innovative deployment of cellular networks by decoupling the multiple layers of signal and protocol processing. This decoupling is crucial as it enables operators to deploy radios from different vendors and integrate them seamlessly into their networks, fostering competition and innovation and enabling lower cost systems. The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. SUMMARY In some example embodiments, a system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, a producer port linked with a consumer port through direct memory access (DMA), wherein data received by the PCIe interface is assigned to the producer port, dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz. In some examples, the PCIe interface is configured to receive the data from a distributed unit of a fronthaul communication system architecture, wherein the distributed unit is in communication with a core network of the communication system. In some examples, the PCIe interface is configured to receive the data from a radio unit of a fronthaul communication system architecture, wherein the radio unit is electrically coupled with at least one cellular antenna, and the radio unit is configured to transmit and receive wireless cellular signals. In some examples, the other wireless communication device includes a second PCIe interface configured to receive data from a second backhaul FPGA of the communication system, a second producer port linked with a second consumer port through DMA, second dual hardware media access controls configured to consume the data assigned to the producer port, and at least one second processor configured to receive, via a second wireless interface, the data transmitted at the frequency of at least sixty Gigahertz. In some examples, the data received by the PCIe interface includes radio over Ethernet (RoE) data. In some examples, the data received from the backhaul FPGA includes enhanced common public radio interface (eCPRI) data, and the backhaul FPGA comprises an eCPRI FPGA. In some examples, the at least one processor is configured to establish control communication channels between the backhaul FPGA and the SoC device through dedicated PCIe ports to central processing unit (CPU) consumer ports. In some examples, the at least one processor is configured to handle lower MAC processes of the SoC device, and the upper MAC processes reside on an application processor of the backhaul FPGA. In some examples, the at least one processor is configured to operate in a de-aggregation mode where an incoming stream of data from the PCIe interface is divided into two radio channel streams using a ping-pong protocol. In some examples, according to the ping-pong protocol, frames of data are sent out in a round-robin manner based on which MAC is able to access the wireless interface. In some examples, each radio channel stream is configured to operate according to a specified modulation rate which allows each MAC to independently request MAC protocol data unit (MPDU) payload from a shared memory space. In some examples, an aggregation layer of the SoC device is configured to synchronize two MACs and reassembly of two independent MAC data streams into a single enhanced common public radio interface (eCPRI) data stream. In some examples, the aggregation layer is configured to reorder out-of-order data frames using 802.11 protocol sequence numbers, c