US-20260129757-A1 - WIRING SUBSTRATE

US20260129757A1US 20260129757 A1US20260129757 A1US 20260129757A1US-20260129757-A1

Abstract

A wiring substrate includes an insulation layer covering a wiring layer, a via hole in the insulation layer, a via wiring filling the via hole, and a wiring layer formed on the insulation layer. The wiring layer includes a metal layer and an adhesion layer formed the metal layer. The adhesion layer includes a wall cover covering a wall surface of at least a lower part of the via hole. The via wiring includes the wall cover, an adhesion layer formed on a wall surface of the via hole to cover an inner surface of the wall cover, a metal film covering the adhesion layer, and a metal layer filling the via hole on an inner side of the metal film. The adhesion layer covering an upper surface of the metal layer is greater in thickness than the adhesion layer covering an upper surface of the insulation layer.

Inventors

Yuki Kobayashi
Takashi Nishiyama
Masaya Takizawa

Assignees

SHINKO ELECTRIC INDUSTRIES CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251029
Priority Date: 20241101

Claims (16)

1 . A wiring substrate, comprising: a first wiring layer; a first insulation layer covering an upper surface of the first wiring layer and a side surface of the first wiring layer; a via hole extending through the first insulation layer in a thickness-wise direction and exposing a portion of the upper surface of the first wiring layer; a via wiring filling the via hole; and a second wiring layer formed integrally with the via wiring and stacked on an upper surface of the first insulation layer, wherein the first wiring layer includes a first metal layer and a first adhesion layer formed on an upper surface of the first metal layer, the first adhesion layer includes a wall cover covering a wall surface of at least a lower part of the via hole, the via wiring includes the wall cover, a second adhesion layer formed on a wall surface of the via hole so as to cover an inner surface of the wall cover, a first metal film covering the second adhesion layer, and a second metal layer filling the via hole on an inner side of the first metal film, the second adhesion layer covers the upper surface of the first insulation layer, and a portion of the first adhesion layer that covers the upper surface of the first metal layer is greater in thickness than a portion of the second adhesion layer that covers the upper surface of the first insulation layer.
2 . The wiring substrate according to claim 1 , wherein the wall cover has a thickness that decreases from a lower end of the wall surface of the via hole toward the upper surface of the first insulation layer.
3 . The wiring substrate according to claim 1 , wherein the second adhesion layer covers the upper surface of the first wiring layer exposed at a bottom of the via hole and covers the wall surface of the via hole exposed from the wall cover.
4 . The wiring substrate according to claim 3 , wherein the upper surface of the first metal layer of the first wiring layer is exposed at the bottom of the via hole, and the second adhesion layer covers the upper surface of the first metal layer exposed at the bottom of the via hole.
5 . The wiring substrate according to claim 3 , wherein an upper surface of the first adhesion layer of the first wiring layer is exposed at the bottom of the via hole, the second adhesion layer covers the upper surface of the first adhesion layer exposed at the bottom of the via hole, and a portion of the first adhesion layer that is exposed at the bottom of the via hole is smaller in thickness than a portion of the first adhesion layer that covers the upper surface of the first metal layer and does not overlap the bottom of the via hole in plan view.
6 . The wiring substrate according to claim 1 , wherein the second adhesion layer exposes a portion of the inner surface of the wall cover, and the first metal film covers entirety of an inner surface of the second adhesion layer and entirety of the inner surface of the wall cover exposed from the second adhesion layer.
7 . The wiring substrate according to claim 3 , wherein the second adhesion layer covers entirety of the inner surface of the wall cover, and the second adhesion layer continuously covers the upper surface of the first wiring layer exposed at the bottom of the via hole, the inner surface of the wall cover, the wall surface of the via hole exposed from the wall cover, and the upper surface of the first insulation layer.
8 . The wiring substrate according to claim 1 , wherein the wall surface of the via hole includes a first wall surface extending downward from the upper surface of the first insulation layer and a recess recessed from the first wall surface to an outer side of the via hole, the recess is formed at the bottom of the via hole, the wall cover covers entirety of a wall surface of the recess, and the via wiring fills the recess.
9 . The wiring substrate according to claim 8 , wherein the recess includes a second wall surface extending from a lower end of the first wall surface toward the outer side of the via hole to an outer end of the recess, the outer end being a most recessed part of the recess, and a third wall surface extending from the outer end to the upper surface of the first wiring layer, the wall cover covers at least a lower part of the first wall surface, the wall cover continuously covers the first wall surface, the second wall surface, the outer end, and the third wall surface, the second adhesion layer exposes a portion of the inner surface of the wall cover, and the second adhesion layer covers the inner surface of the wall cover on at least an upper end part of a portion of the wall cover covering the first wall surface and also covers entirety of the first wall surface exposed from the wall cover, and the first metal film covers entirety of an inner surface of the second adhesion layer and exposes a portion of the inner surface of the wall cover.
10 . The wiring substrate according to claim 9 , wherein the second wall surface is inclined upward from the lower end of the first wall surface toward the outer end, and the third wall surface is inclined toward an inner side of the via hole as the third wall surface extends from the outer end toward the upper surface of the first wiring layer.
11 . The wiring substrate according to claim 1 , wherein the first wiring layer includes a third adhesion layer, a second metal film covering an upper surface of the third adhesion layer, the first metal layer covering an upper surface of the second metal film, and the first adhesion layer, and a portion of the first adhesion layer that covers the upper surface of the first metal layer is greater in thickness than the third adhesion layer.
12 . The wiring substrate according to claim 1 , wherein the second wiring layer includes the second adhesion layer covering the upper surface of the first insulation layer, the first metal film covering the upper surface of the second adhesion layer, a third metal layer formed on the upper surface of the first metal film, and a fourth adhesion layer formed on an upper surface of the third metal layer, and a portion of the fourth adhesion layer that covers the upper surface of the third metal layer is greater in thickness than a portion of the second adhesion layer that covers the upper surface of the first insulation layer.
13 . The wiring substrate according to claim 1 , wherein the wall cover of the first adhesion layer is formed continuously and integrally with the portion of the first adhesion layer that covers the upper surface of the first metal layer.
14 . The wiring substrate according to claim 1 , wherein the wall cover of the first adhesion layer and the second adhesion layer directly cover the wall surface of the via hole while partially overlapping each other on the wall surface of the via hole.
15 . The wiring substrate according to claim 1 , wherein the portion of the first adhesion layer that covers the upper surface of the first metal layer is greater in thickness than each of the wall cover and the second adhesion layer.
16 . The wiring substrate according to claim 1 , wherein the via wiring includes a seed layer covering the wall surface of the via hole, and the second metal layer formed on the seed layer and filling the via hole, the seed layer has a multilayer structure in which a combination of layers changes from an upper end of the wall surface of the via hole to a lower end of the wall surface of the via hole, wherein at the upper end of the wall surface of the via hole, the seed layer has a two-layer structure comprising the first metal film and the second adhesion layer, and at the lower end of the wall surface of the via hole, the seed layer has a two-layer or three-layer structure comprising the first metal film and at least one of the wall cover and the second adhesion layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from Japanese Patent Applications No. 2024-192684, filed on Nov. 1, 2024 and No. 2025-042327, filed on Mar. 17, 2025, the entire contents of which are incorporated herein by reference. BACKGROUND 1. Field This disclosure relates to a wiring substrate and a method for manufacturing a wiring substrate. 2. Description of Related Art Wiring substrates on which electronic components such as semiconductor elements are mounted have various shapes and various structures. JP2021-168348A discloses an example of such a wiring substrate formed by a build-up process that alternately stacks wiring layers and insulation layers. The wiring layers are electrically connected to each other by via wirings that are formed in through holes extending through the insulation layers in a thickness-wise direction. SUMMARY It is desirable that the electrical connection reliability of the above-described wiring substrate be improved. In an aspect of the present disclosure, a wiring substrate includes a first wiring layer, a first insulation layer covering an upper surface and a side surface of the first wiring layer, a via hole extending through the first insulation layer in a thickness-wise direction and exposing a portion of the upper surface of the first wiring layer, a via wiring filling the via hole, and a second wiring layer formed integrally with the via wiring and stacked on an upper surface of the first insulation layer. The first wiring layer includes a first metal layer and a first adhesion layer formed on an upper surface of the first metal layer. The first adhesion layer includes a wall cover covering a wall surface of at least a lower part of the via hole. The via wiring includes the wall cover, a second adhesion layer formed on a wall surface of the via hole so as to cover an inner surface of the wall cover, a first metal film covering the second adhesion layer, and a second metal layer filling the via hole on an inner side of the first metal film. The second adhesion layer covers the upper surface of the first insulation layer. A portion of the first adhesion layer that covers the upper surface of the first metal layer is greater in thickness than a portion of the second adhesion layer that covers the upper surface of the first insulation layer. Other features and aspects will be apparent from the following detailed description, the drawings, and the claims. This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view illustrating a wiring substrate in accordance with some embodiment. FIG. 2 is a schematic cross-sectional view illustrating, in an enlarged manner, part of the wiring substrate in accordance with a first embodiment. FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17 are schematic cross-sectional views illustrating a method for manufacturing the wiring substrate of FIG. 2. FIG. 18 is a schematic cross-sectional view illustrating a structure of a sample used in a test. FIGS. 19A and 19B are graphs illustrating test results. FIG. 20 is a schematic cross-sectional view illustrating, in an enlarged manner, part of a wiring substrate in accordance with a second embodiment. FIGS. 21, 22, 23, 24, and 25 are schematic cross-sectional views illustrating a method for manufacturing the wiring substrate of FIG. 20. FIGS. 26, 27, and 28 are schematic cross-sectional views illustrating wiring substrates of various modified examples. Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION This description provides a comprehensive understanding of the methods, apparatuses, and/or systems described. Modifications and equivalents of the methods, apparatuses, and/or systems described are apparent to one of ordinary skill in the art. Sequences of operations are exemplary, and may be changed as apparent to one of ordinary skill in the art, with the exception of operations necessarily occurring in a certain order. Descriptions of functions and constructions that are well known to one of ordinary skill in the art may be omitted. Exemplary embodiments may have different forms, and are not limited to the examples described. However, the examples described are thorough and complete, and convey the full scope of the disclosure to one of ordinary skill in the art. In this specification, “at least one of A and B” shoul