US-20260129819-A1 - Static random access memory structure and manufacturing method thereof

US20260129819A1US 20260129819 A1US20260129819 A1US 20260129819A1US-20260129819-A1

Abstract

The invention provides a static random access memory structure, which comprises a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected with the silicon substrate and protruding from the shallow trench isolation, a first gate structure spanning the first fin structure and parts of the shallow trench isolation, so that the first gate structure covers a top surface and a part of sidewalls of the first fin structure, and forms a pass gate transistor (PG). And a protruding part located directly below the first gate structure and on the shallow trench isolation, the protruding part covers part of the surface of at least one sidewall of the first fin structure, and a top surface of the protruding part is higher than a top surface of the shallow trench isolation.

Inventors

Chun-Hsien Huang
Chien-Hung Chen
Yu-Tse Kuo
Shu-Ru Wang
Chun-Yen TSENG

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260507
Application Date: 20241204
Priority Date: 20241106

Claims (20)

1 . A static random access memory structure, comprising: a silicon substrate; a shallow trench isolation located on the silicon substrate; a first fin structure connected to the silicon substrate and protruding from the shallow trench isolation; a first gate structure across the first fin structure and part of the shallow trench isolation, so that the first gate structure covers a top surface and part of sidewalls of the first fin structure, and constitutes a pass gate transistor (PG) of the SRAM; and a protrusion part located directly below the first gate structure and on the shallow trench isolation, covering part of the surface of at least one sidewall of the first fin structure, wherein a top surface of the protrusion part is higher than a top surface of the shallow trench isolation, and a height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and a height from the top surface of the shallow trench isolation to the top surface of the protrusion part in the vertical direction is defined as h2.
2 . The SRAM structure according to claim 1 , wherein, when viewed from a cross section view, the protrusion part covers part of the surface of both sidewalls of the first fin structure, wherein a width of the top surface of the first fin structure is defined as w1, and the effective channel width of the pass gate transistor formed by the first gate structure covering the first fin structure is w1+2 (h1−h2).
3 . The SRAM structure according to claim 1 , wherein viewed from a cross section view, the protrusion part only covers part of the surface of one sidewall of the first fin structure, wherein a width of the top surface of the first fin structure is defined as w1, and the effective channel width of the pass gate transistor formed by the first gate structure covering the first fin structure is w1+2h1−h2.
4 . The SRAM structure according to claim 1 , further comprising: a second fin structure connected to the silicon substrate and protruding from the shallow trench isolation; and a second gate structure across the second fin structure and part of the shallow trench isolation, so that the second gate structure covers a top surface and part of sidewalls of the second fin structure, and constitutes a pull-down transistor (PD) of the SRAM.
5 . The SRAM structure according to claim 4 , wherein the protrusion part is not included between a region directly below the second gate structure and the shallow trench isolation, wherein the top surface of the first fin structure and the top surface of the second fin structure are aligned with each other in a horizontal direction, and a bottom surface of the first fin structure and a bottom surface of the second fin structure are aligned with each other in the horizontal direction.
6 . The SRAM structure according to claim 5 , wherein a width of the top surface of the second fin structure is defined as w1, a height from the top surface of the shallow trench isolation to the top surface of the second fin structure in the vertical direction is defined as h1, and the effective channel width of the pull-down transistor formed by the second gate structure covering the second fin structure is w1+2h1.
7 . The SRAM structure according to claim 1 , wherein the condition of 0<h2/h1<0.5 is satisfied.
8 . The SRAM structure according to claim 1 , wherein the material of the protrusion part is different from the material of the shallow trench isolation.
9 . The SRAM structure according to claim 1 , wherein the material of the protrusion part is the same as the material of the shallow trench isolation, and the protrusion part and the shallow trench isolation are integrally formed structure.
10 . A method for fabricating a static random access memory structure, comprising: providing a silicon substrate; forming a shallow trench isolation on the silicon substrate; forming a first fin structure connected to the silicon substrate and protruding from the shallow trench isolation; forming a first gate structure across the first fin structure and part of the shallow trench isolation, so that the first gate structure covers a top surface and part of sidewalls of the first fin structure, and constitutes a pass gate transistor (PG) of the SRAM; and forming a protrusion part directly below the first gate structure and on the shallow trench isolation, covering part of the surface of at least one sidewall of the first fin structure, wherein a top surface of the protrusion part is higher than a top surface of the shallow trench isolation, and a height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and a height from the top surface of the shallow trench isolation to the top surface of the protrusion part in the vertical direction is defined as h2.
11 . The manufacturing method of the SRAM structure according to claim 10 , wherein when viewed from a cross section view, the protrusion part covers part of the surface of both sidewalls of the first fin structure, wherein a width of the top surface of the first fin structure is defined as w1, and the effective channel width of the pass gate transistor formed by the first gate structure covering the first fin structure is w1+2 (h1−h2).
12 . The manufacturing method of the SRAM structure according to claim 10 , wherein viewed from a cross section view, the protrusion part only covers part of the surface of one sidewall of the first fin structure, wherein a width of the top surface of the first fin structure is defined as w1, and the effective channel width of the pass gate transistor formed by the first gate structure covering the first fin structure is w1+2h1−h2.
13 . The method for manufacturing the SRAM structure according to claim 10 , further comprising: forming a second fin structure connected to the silicon substrate and protruding from the shallow trench isolation; and forming a second gate structure across the second fin structure and part of the shallow trench isolation, so that the second gate structure covers a top surface and part of sidewalls of the second fin structure, and constitutes a pull-down transistor (PD) of the SRAM.
14 . The manufacturing method of the SRAM structure according to claim 13 , wherein the protrusion part is not included between a region directly below the second gate structure and the shallow trench isolation, wherein the top surface of the first fin structure and the top surface of the second fin structure are aligned with each other in a horizontal direction, and a bottom surface of the first fin structure and a bottom surface of the second fin structure are aligned with each other in the horizontal direction.
15 . The manufacturing method of the SRAM structure according to claim 14 , wherein a width of the top surface of the second fin structure is defined as w1, a height from the top surface of the shallow trench isolation to the top surface of the second fin structure in the vertical direction is defined as h1, and the effective channel width of the pull-down transistor formed by the second gate structure covering the second fin structure is w1+2h1.
16 . The method for manufacturing a SRAM structure according to claim 10 , wherein the condition of 0<h2/h1<0.5 is satisfied.
17 . The manufacturing method of the SRAM structure according to claim 10 , wherein the material of the protrusion part is different from the material of the shallow trench isolation.
18 . The method for manufacturing the SRAM structure according to claim 17 , wherein the method for forming the protrusion part comprises: forming a material layer on the shallow trench isolation after the shallow trench isolation is formed; performing a patterning step to remove part of the material layer, and defining the remaining material layer as the protruding part.
19 . The manufacturing method of the SRAM structure according to claim 10 , wherein the material of the protrusion part is the same as the material of the shallow trench isolation, and the protrusion part and the shallow trench isolation are integrally formed structure.
20 . The method for manufacturing the SRAM structure according to claim 19 , wherein the method for forming the protrusion part comprises: forming a mask layer on the shallow trench isolation after the shallow trench isolation is formed; performing a patterning step to remove part of the shallow trench isolation not covered by the mask layer, and defining a part of the shallow trench isolation covered by the mask layer as the protrusion part.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a static random access memory (SRAM), in particular to a layout pattern of a static random access memory (SRAM) with high efficiency and a manufacturing method thereof. 2. Description of the Prior Art An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer systems as a cache memory. SUMMARY OF THE INVENTION The invention provides a static random access memory structure. The static random access memory structure includes a silicon substrate, a shallow trench isolation located on the silicon substrate, a first fin structure connected to the silicon substrate and protruding from the shallow trench isolation, a first gate structure across the first fin structure and part of the shallow trench isolation, so that the first gate structure covers a top surface and part of sidewalls of the first fin structure, and constitutes a pass gate transistor (PG) of the SRAM, and a protrusion part located directly below the first gate structure and on the shallow trench isolation, covering part of the surface of at least one sidewall of the first fin structure, wherein a top surface of the protrusion part is higher than a top surface of the shallow trench isolation, and a height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and a height from the top surface of the shallow trench isolation to the top surface of the protrusion part in the vertical direction is defined as h2. The invention also provides a method for manufacturing a static random access memory structure, which includes the following steps: providing a silicon substrate, forming a shallow trench isolation on the silicon substrate, forming a first fin structure connected to the silicon substrate and protruding from the shallow trench isolation, forming a first gate structure across the first fin structure and part of the shallow trench isolation, so that the first gate structure covers a top surface and part of sidewalls of the first fin structure, and constitutes a pass gate transistor (PG) of the SRAM, and forming a protrusion part directly below the first gate structure and on the shallow trench isolation, covering part of the surface of at least one sidewall of the first fin structure, wherein a top surface of the protrusion part is higher than a top surface of the shallow trench isolation, and a height from the top surface of the shallow trench isolation to the top surface of the first fin structure in a vertical direction is defined as h1, and a height from the top surface of the shallow trench isolation to the top surface of the protrusion part in the vertical direction is defined as h2. The invention is characterized in that in order to improve the device quality, it is necessary to increase the ratio of the turn-on current of the PD transistor to the turn-on current of the PG transistor, but the width of the fin structure formed by sidewall pattern transfer cannot be adjusted only by the mask pattern. Therefore, the invention adjusts the channel width of the transistor by changing the shallow trench isolation around the fin structure or the height of the protrusion part. More specifically, the invention uses etching process to reduce shallow trench isolation beside other transistors except the PG transistor, or uses another mask layer to cover the PG fin structure, so that when the gate structure is covered on the fin structure, the channel width of the PD transistor will be larger the channel width of the PG transistor, thereby reducing the turn-on current of the PG transistor and achieving the purpose of improving the beta value and static noise margin of SRAM. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the following easier to understand, readers can refer to the drawings and their detailed descriptions at the same time when reading the present invention. Through the specific embodiments in the present specification and referring to the corresponding drawings, the specific embodiments of the present invention will be explained in detail, and the working principle of the specific embodiments of the present invention will be expounded. In addition, for the sake of clarity, the features in the d