US-20260129821-A1 - SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME

US20260129821A1US 20260129821 A1US20260129821 A1US 20260129821A1US-20260129821-A1

Abstract

Semiconductor devices and methods are provided. An exemplary method includes receiving a transistor comprising a gate structure over a channel region, first and second source/drain features coupled to the channel region, and a dielectric structure over the first and the second source/drain features; forming a first trench extending through the dielectric structure to expose the first source/drain feature and a second trench extending through the dielectric structure to expose the second source/drain feature; forming a mask layer covering the first trench, wherein an opening of the mask layer exposes a portion of the second trench; after the forming of the mask layer, performing an ion implantation process to form a doped region in the second source/drain feature; and after the performing of the ion implantation process, forming a first source/drain contact in the first trench and a second source/drain contact in the second trench.

Inventors

Jui-Lin Chen
Yung-Ting Chang
Yu-Bey Wu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A semiconductor device, comprising: a memory cell comprising: a write port portion; and a read port portion electrically coupled to the write port portion and comprising a p-type transistor (R-PG) having: a first source/drain feature having one or more epitaxial layers including p-type dopant, a second source/drain feature substantially the same as the first source/drain feature, and a p-type doped region extended into the one or more epitaxial layers of the first source/drain feature.
2 . The semiconductor device of claim 1 , wherein the p-type dopant comprises a combination of Boron- 11 isotope and Boron- 10 isotope.
3 . The semiconductor device of claim 1 , wherein the p-type doped region comprises Boron-11 isotope, germanium (Ge) or gallium (Ga).
4 . The semiconductor device of claim 1 , wherein the p-type doped region is disposed in a top portion of the first source/drain feature, and the p-type transistor further comprises a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature, wherein a bottom surface of the p-type doped region is lower than a bottom surface of a topmost nanostructure of the plurality of nanostructures.
5 . The semiconductor device of claim 1 , further comprising: a source/drain contact disposed over and electrically coupled to the first source/drain feature, wherein a center line of the source/drain contact is offset from a center line of the doped region.
6 . The semiconductor device of claim 1 , wherein the p-type transistor is a first p-type transistor, the p-type doped region is a first p-type doped region, and the write port portion comprises a second p-type transistor having: the first source/drain feature, a third source/drain feature, and a second p-type doped region in the third source/drain feature, wherein the second p-type doped region spans a depth greater than the first p-type doped region.
7 . The semiconductor device of claim 6 , wherein the write port portion further comprises a third p-type transistor having: the third source/drain feature, the second p-type doped region in the third source/drain feature, a fourth source/drain feature, and a third p-type doped region in the fourth source/drain feature, wherein the third p-type doped region is substantially the same as the second p-type doped region.
8 . The semiconductor device of claim 6 , wherein saturation current of the second p-type transistor is greater than saturation current of the first p-type transistor.
9 . The semiconductor device of claim 1 , wherein the memory cell is a seven-transistor static random access memory (SRAM) cell or an eight-transistor static random access memory (SRAM) cell.
10 . A semiconductor device, comprising: a first p-type transistor comprising a first gate structure disposed over a first portion of an active region; and a second p-type transistor comprising a second gate structure disposed over a second portion of the active region, wherein the second p-type transistor comprises a first source/drain feature having a first dopant concentration and a second source/drain feature having a second dopant concentration greater than the first dopant concentration.
11 . The semiconductor device of claim 10 , wherein a concentration of Boron- 11 isotope in the first source/drain feature is less than a concentration of Boron- 11 isotope in the second source/drain feature, and a concentration of Boron- 10 isotope in the first source/drain feature is equal to a concentration of Boron- 10 isotope in the second source/drain feature.
12 . The semiconductor device of claim 10 , wherein the first transistor comprises the second source/drain feature and a third source/drain feature having a dopant concentration greater than the second dopant concentration.
13 . The semiconductor device of claim 12 , wherein the second source/drain feature comprises a doped epitaxial region having a first dopant and a first doped region extended into the doped epitaxial region and having a second dopant, wherein the third source/drain feature comprises another doped epitaxial region having the first dopant and a second doped region extended into the another doped epitaxial region and having the second dopant, wherein the second doped region spans a depth greater than a depth of the first doped region.
14 . The semiconductor device of claim 13 , wherein the first portion of the active region is disposed directly under the first gate structure and comprises a plurality of nanostructures, wherein a depth of the second doped region is lower than a bottom surface of a topmost nanostructure of the plurality of nanostructures.
15 . The semiconductor device of claim 10 , wherein the second source/drain feature comprises: an epitaxial region having a top surface and a bottom surface; a first doped region adjacent to the top surface of the epitaxial region; and a second doped region adjacent to the bottom surface of the epitaxial region and disposed under the first doped region.
16 . The semiconductor device of claim 10 , further comprising: a first silicide layer contacting the first source/drain feature at a first interface; and a second silicide layer contacting the second source/drain feature at a second interface, wherein a concentration of Boron- 11 isotope of the second interface is greater than a concentration of Boron- 11 isotope of the first interface.
17 . A method, comprising: receiving a transistor comprising: a gate structure over a channel region, a first source/drain feature and a second source/drain feature coupled to the channel region, and a dielectric structure over the first source/drain feature and the second source/drain feature; forming a first trench extending through the dielectric structure to expose the first source/drain feature and a second trench extending through the dielectric structure to expose the second source/drain feature; forming a mask layer covering the first trench, wherein an opening of the mask layer exposes a portion of the second trench; after the forming of the mask layer, performing an ion implantation process to form a doped region in the second source/drain feature; and after the performing of the ion implantation process, forming a first source/drain contact in the first trench and a second source/drain contact in the second trench.
18 . The method of claim 17 , wherein the transistor is a p-type transistor, and the performing of the ion implantation process comprises implanting p-type dopants.
19 . The method of claim 17 , wherein the channel region comprises a plurality of nanostructures, and the gate structure further wraps around the plurality of nanostructures.
20 . The method of claim 17 , wherein a center line of the doped region is offset from a center line of the second source/drain feature.

Description

BACKGROUND In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. The amount of embedded SRAM in microprocessors and SOCs increases to meet the performance requirement in each new technology generation. Performances of transistors in an SRAM cell may affect a minimum operating voltage (Vmin) of the SRAM cell. This may lead to sub-par SRAM performance or even device failures. Therefore, although existing memory devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a diagrammatic plan view of an IC chip, in portion or entirety, according to various aspects of the present disclosure. FIG. 1B is a diagrammatic plan view of an array of memory cells, such as static random-access memory (SRAM) cells, in portion or entirety, according to various aspects of the present disclosure. FIG. 2 is a circuit diagram of a memory cell, such as an SRAM cell, that can be implemented in the IC chip of FIG. 1, according to various aspects of the present disclosure. FIG. 3 illustrates a fragmentary layout of a memory device including the SRAM cell, according to various aspects of the present disclosure. FIG. 4 illustrates a flow chart of a method for forming a memory device including the SRAM cell, according to one or more aspects of the present disclosure. FIGS. 5, 6, 11, 12, 13 illustrate fragmentary top views of the memory device during various fabrication stages in the method of FIG. 4, according to one or more aspects of the present disclosure. FIGS. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 17, 18 illustrate fragmentary cross-sectional views of the memory device taken along line A-A shown in FIG. 3 or line A′-A′ shown in FIG. 6 during various fabrication stages in the method of FIG. 4, according to one or more aspects of the present disclosure. FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B illustrate fragmentary layouts and/or cross-sectional views of the memory device taken along line B-B shown in FIG. 6 during various fabrication stages in the method of FIG. 4, according to one or more aspects of the present disclosure. FIGS. 11C, 12C, 13C, 14C, 15C illustrate fragmentary layouts and/or cross-sectional views of the memory device taken along line C-C shown in FIG. 6 during various fabrication stages in the method of FIG. 4, according to one or more aspects of the present disclosure. FIG. 16 illustrates a dopant concentration profile of a doped region over a range of depths in source/drain features, according to one or more aspects of the present disclosure. FIG. 19 illustrates a flow chart of a method for forming a first alternative memory device including the SRAM cell, according to one or more aspects of the present disclosure. FIG. 20 illustrates a fragmentary layout of the first alternative memory device, according to one or more aspects of the present disclosure. FIGS. 21, 22, 23, 24, 25, 26 illustrate fragmentary cross-sectional views of the first alternative memory device taken along line A-A and/or D-D shown in FIG. 20 during various fabrication stages in the method of FIG. 19, according to one or more aspects of the present disclosure. FIG. 27 illustrates a fragmentary cross-sectional view of a second memory device taken along line A-A, according to one or more aspects of the present disclosure. FIG. 28 illustrates dopant concentration profiles of a first doped region and a second doped region over a range of depths in source/drain features, according to one or more aspects of the present disclosure. FIG. 29 illustrates a fragmentary layout of a third alternative memory device, according to one or more aspects of the present disclosure. FIG. 30 illustrates a fragmentary cross-sectional view of the third memory device taken along line E-E, according to one or more aspects of the present disclosure. FIG. 31 illustrates a fragmentary cross-sectional view of the third memory device taken along line F-F, according to one or more aspects of the present disclosure. FIGS. 32 and 33 each illustrate a fragmentary top view of a fourth alternative memory device and a fifth alternative memory device, respectively, according to one or more aspects of the present disclosure. FIG. 34 illustrates a fragmentary layout of the IC chip, according to one or more aspects of the present disclosure. FIG. 35 is a circuit diagram of a different memory cell, such