US-20260129822-A1 - MEMORY DEVICE

US20260129822A1US 20260129822 A1US20260129822 A1US 20260129822A1US-20260129822-A1

Abstract

A memory device includes a first static random access memory (SRAM) cell, a second SRAM cell, and a first metal layer. The first SRAM cell includes first read-port pass-gate (PG) and pull-down (PD) transistors arranged in a Y-direction, and second read-port PG and PD transistors arranged in the Y-direction. The first and second read-port PD transistors share a first gate structure extending in an X-direction. The second SRAM cell includes third read-port PG and PD transistors arranged in the Y-direction, and fourth read-port PG and PD transistors arranged in the Y-direction. The third and fourth read-port PD transistors share a second gate structure extending in the X-direction. The first metal layer is over the first and second SRAM cells. The first metal layer includes first and second read bit-line conductors extending in the Y-direction and shared by the first and second SRAM cells.

Inventors

Jhon-Jhy Liaw

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20260105

Claims (20)

1 . A device, comprising: a first transistor of a first cell, a second transistor of the first cell, a third transistor of a second cell, and a fourth transistor of the second cell arranged in a first direction; a fifth transistor of the first cell, a sixth transistor of the first cell, a seventh transistor of the second cell, and an eighth transistor of the second cell arranged in the first direction; and a first metal layer comprising: a first signal conductor electrically coupled to the first transistor and the fourth transistor; and a second signal conductor electrically coupled to the fifth transistor and the eighth transistor.
2 . The device of claim 1 , wherein the first signal conductor is electrically connected to a source/drain feature of the first transistor and a source/drain feature of the fourth transistor, wherein the second signal conductor is electrically connected to a source/drain feature of the fifth transistor and a source/drain feature of the eighth transistor.
3 . The device of claim 2 , wherein the first cell has a first non-rectangular cell boundary in a top view and the second cell has a second non-rectangular cell boundary in the top view.
4 . The device of claim 3 , comprising: a first source/drain contact and a second source/drain contact extending in a second direction, lengthwise overlapping the first non-rectangular cell boundary, and being respectively over a source/drain feature of the first transistor and a source/drain feature of the fifth transistor; and a third source/drain contact and a fourth source/drain contact extending in the second direction, lengthwise overlapping the second non-rectangular cell boundary, and being respectively over a source/drain feature of the fourth transistor and a source/drain feature of the eighth transistor, wherein the first signal conductor is electrically connected to the first source/drain contact and the third source/drain contact, and the second signal conductor is electrically connected to the second source/drain contact and the fourth source/drain contact.
5 . The device of claim 1 , wherein the first cell comprises: a ninth transistor and a tenth transistor arranged in the first direction; and an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor arranged in the first direction, wherein the second cell further comprises: a fifteenth transistor and a sixteenth transistor arranged in the first direction; and a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor arranged in the first direction, wherein the ninth transistor and the eleventh transistor share a first gate structure, wherein the fifteenth transistor and the seventeenth transistor share a second gate structure.
6 . The device of claim 5 , wherein the first metal layer comprises a first metal conductor and a second metal conductor extending in the first direction and electrically coupled to a voltage source, wherein the first metal conductor is electrically connected to a source/drain feature shared by the ninth transistor and the tenth transistor, wherein the second metal conductor is electrically connected to a source/drain feature shared by the fifteenth transistor and the sixteenth transistor.
7 . The device of claim 5 , further comprising: a second metal layer over the first metal layer, wherein the second metal layer comprises a third signal conductor and a fourth signal conductor extending in a second direction, wherein the third signal conductor is electrically connected to a gate structure of the first transistor, wherein the fourth signal conductor is electrically connected to a gate structure of the eighth transistor.
8 . The device of claim 7 , further comprising: a third metal layer over the second metal layer, wherein the third metal layer comprises a fifth signal conductor, a sixth signal conductor, a seventh signal conductor, and an eighth signal conductor extending in the first direction, wherein the fifth signal conductor is electrically connected to a source/drain feature of the thirteenth transistor, wherein the sixth signal conductor is electrically connected to a source/drain feature of the nineteenth transistor, wherein the seventh signal conductor is electrically connected to a source/drain feature of the fourteenth transistor, wherein the eighth signal conductor is electrically connected to a source/drain feature of the twentieth transistor.
9 . The device of claim 8 , further comprising: a fourth metal layer over the third metal layer, wherein the fourth metal layer comprises a ninth signal conductor and a tenth signal conductor extending in the second direction, wherein the ninth signal conductor is electrically connected to a gate structure of the fifth transistor, wherein the tenth signal conductor is electrically connected to a gate structure of the fourth transistor.
10 . The device of claim 9 , further comprising: a fifth metal layer over the fourth metal layer, wherein the fifth metal layer comprises an eleventh signal conductor and a twelfth signal conductor extending in the second direction, wherein the eleventh signal conductor is electrically connected to gate structures of the thirteenth transistor and the fourteenth transistor, wherein the twelfth signal conductor is electrically connected to gate structures of the nineteenth transistor and the twentieth transistor.
11 . A method, comprising: forming a first active area and a second active area offset from each other along a first direction; forming a first transistor of a first cell, a second transistor of the first cell, a third transistor of a second cell, and a fourth transistor of the second cell arranged on the first active area in a second direction different than the first direction; forming a fifth transistor of the first cell, a sixth transistor of the first cell, a seventh transistor of the second cell, and an eighth transistor of the second cell arranged on the second active area in the second direction; forming a first signal conductor electrically coupled to the first transistor and the fourth transistor; and forming a second signal conductor electrically coupled to the fifth transistor and the eighth transistor.
12 . The method of claim 11 , wherein forming the first signal conductor comprises forming the first signal conductor electrically connected to a source/drain feature of the first transistor and a source/drain feature of the fourth transistor, wherein forming the second signal conductor comprises forming the second signal conductor electrically connected to a source/drain feature of the fifth transistor and a source/drain feature of the eighth transistor.
13 . The method of claim 12 , wherein forming the first transistor comprises forming the first transistor of the first cell, the first cell having a first non-rectangular cell boundary in a top view; and wherein forming the third transistor comprises forming the third transistor of the second cell, the second cell having a second non-rectangular cell boundary in the top view.
14 . The method of claim 13 , comprising: forming a first source/drain contact and a second source/drain contact extending in a second direction, lengthwise overlapping the first non-rectangular cell boundary, and being respectively over a source/drain feature of the first transistor and a source/drain feature of the fifth transistor; and forming a third source/drain contact and a fourth source/drain contact extending in the second direction, lengthwise overlapping the second non-rectangular cell boundary, and being respectively over a source/drain feature of the fourth transistor and a source/drain feature of the eighth transistor, wherein forming the first signal conductor comprises forming the first signal conductor electrically connected to the first source/drain contact and the third source/drain contact, and wherein forming the second signal conductor comprises forming the second signal conductor electrically connected to the second source/drain contact and the fourth source/drain contact.
15 . The method of claim 11 , comprising: forming a ninth transistor and a tenth transistor of the first cell arranged in the first direction; forming an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor of the first cell arranged in the first direction, forming a fifteenth transistor and a sixteenth transistor of the second cell arranged in the first direction; and forming a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor of the second cell arranged in the first direction, wherein the ninth transistor and the eleventh transistor share a first gate structure, wherein the fifteenth transistor and the seventeenth transistor share a second gate structure.
16 . The method of claim 15 , comprising: forming a first metal layer having a first metal conductor and a second metal conductor extending in the first direction and electrically coupled to a voltage source, wherein the first metal conductor is electrically connected to a source/drain feature shared by the ninth transistor and the tenth transistor, wherein the second metal conductor is electrically connected to a source/drain feature shared by the fifteenth transistor and the sixteenth transistor.
17 . A device, comprising: a first cell, comprising: a ninth transistor and a tenth transistor arranged in a first direction; an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor arranged in the first direction; a first transistor and a second transistor; and a fifth transistor and a sixth transistor, wherein the ninth transistor, the eleventh transistor, the second transistor, and the sixth transistor share a first gate structure extending in a second direction; a second cell abutted to the first cell, comprising: a fifteenth transistor and a sixteenth transistor arranged in the first direction; a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor arranged in the first direction; a fourth transistor and a third transistor; and a eighth transistor and a seventh transistor, wherein the fifteenth transistor, the seventeenth transistor, the third transistor, and the seventh transistor share a second gate structure extending in the second direction, wherein the first transistor, the second transistor, the fourth transistor, and the third transistor are arranged in the first direction, wherein the fifth transistor, the sixth transistor, the eighth transistor, and the seventh transistor are arranged in the first direction; and a first signal conductor and a second signal conductor extending in the first direction and shared by the first cell and the second cell.
18 . The device of claim 17 , wherein the first cell has a first L-shaped cell boundary in a top view and the second cell has a second L-shaped cell boundary in the top view.
19 . The device of claim 18 , wherein the first L-shaped cell boundary and the second L-shaped cell boundary combine to form a rectangle.
20 . The device of claim 19 , wherein a dimension of the rectangle in the second direction is greater than a dimension of the rectangle in the first direction.

Description

RELATED APPLICATIONS This is a continuation application of pending U.S. patent application Ser. No. 18/315,023, titled “MEMORY DEVICE” and filed May 10, 2023. U.S. patent application Ser. No. 18/315,023 is herein incorporated by reference in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed. As integrated circuit (IC) technologies progress towards smaller technology nodes, fin field-effect transistors (FinFETs) and gate-all-around (GAA) transistors have been incorporated into memory devices (including, for example, static random-access memory, or SRAM, cells) to reduce chip footprint while maintaining reasonable processing margins. However, as memory devices continue to be scaled down, the interconnection routing for memory devices uses too many routing resources and therefore impacts the cell scaling as well as memory performance. Accordingly, although existing technologies for fabricating memory devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a fragmentary diagrammatic top view of an integrated circuit (IC) chip, in portion or entirety, in accordance with some embodiments of the present disclosure. FIG. 2 is a circuit diagram for an SRAM cell that can be implemented in an array of three-port SRAM cells in the memory region of FIG. 1, in accordance with some alternative embodiments of the present disclosure. FIG. 3 is a circuit diagram for two SRAM cells that can be implemented in adjacent two rows of an array of three-port SRAM cells in the memory region of FIG. 1, in accordance with some alternative embodiments of the present disclosure. FIG. 4 is a perspective view of a GAA transistor in the SRAM cell, in accordance with some embodiments of the present disclosure. FIG. 5 is a cross sectional view of a memory device for illustrating an interconnection structure, in accordance with some embodiments of the present disclosure. FIGS. 6A, 6B, 6C, 6D, 6E, and 6F are top views (or layouts) of two SRAM cells in adjacent two rows of an array in a portion of the array that can be one embodiment of three-port SRAM cells implemented in the memory region, in accordance with some embodiments of the present disclosure. FIG. 6G is a cross-sectional view of the array along a line A-A′ in FIG. 6A, in accordance with some embodiments of the present disclosure. FIG. 6H is a cross-sectional view of the array along a line B-B′ in FIG. 6A, in accordance with some embodiments of the present disclosure. FIG. 6I is a cross-sectional view of the array along a line C-C′ in FIG. 6A, in accordance with some embodiments of the present disclosure. FIG. 7A is a top view (or a layout) of two SRAM cells in adjacent two rows of an array in a portion of an array that can be one embodiment of three-port SRAM cells implemented in the memory region, in accordance with some embodiments of the present disclosure. FIG. 7B is a cross-sectional view of the array along a line A-A′ in FIG. 7A, in accordance with some embodiments of the present disclosure. FIG. 8A is a top view (or a layout) of two SRAM cells in adjacent two rows of an array in a portion of an array that can be one embodiment of three-port SRAM cells implemented in the memory region, in accordance with some embodiments of the present disclosure. FIG. 8B is a cross-sectional view of the array along a line A-A′ in FIG. 8A, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be