US-20260129823-A1 - SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREFOR

US20260129823A1US 20260129823 A1US20260129823 A1US 20260129823A1US-20260129823-A1

Abstract

The forming method for a semiconductor structure includes following operations. A substrate is provided. The substrate includes a memory region and a boundary region sequentially adjacent to each other. An initial conductive layer is formed on the substrate and is patterned to form multiple initial bit line structures and an initial bit line contact layer. An etching mask provided with multiple first openings is formed. The initial bit line structures and the initial bit line contact layer are patterned by employing the etching mask to form multiple bit line structures and multiple bit line contact pads. Bit line isolation structures are formed. Each bit line isolation structure includes a first isolation portion located between the bit line structures and a second isolation portion located between the bit line contact pads. A first width of the first isolation portion is greater than a second width of the second isolation portion.

Inventors

Kanyu Cao
Wangrong GAO
Lingxiang WANG

Assignees

CXMT Corporation

Dates

Publication Date: 20260507
Application Date: 20251218
Priority Date: 20241104

Claims (14)

1 . A forming method for a semiconductor structure, comprising: providing a substrate, the substrate comprising a memory region and a boundary region sequentially adjacent to each other, and the memory region comprising an array region and a dummy region; forming an initial conductive layer on the substrate; patterning the initial conductive layer in the memory region to form a plurality of initial bit line structures, and retaining the initial conductive layer in the boundary region to form an initial bit line contact layer, the plurality of initial bit line structures extending in a first direction and being arranged at intervals in a second direction; forming an etching mask provided with a plurality of first openings, the plurality of first openings exposing a part of the initial bit line structures in the dummy region and a part of the initial bit line contact layer in the boundary region; patterning the initial bit line structures and the initial bit line contact layer by employing the etching mask to form a plurality of bit line structures and a plurality of bit line contact pads; and forming bit line isolation structures, each of the bit line isolation structures comprising a first isolation portion located between the bit line structures and a second isolation portion located between the bit line contact pads, and a first width of the first isolation portion being greater than a second width of the second isolation portion.
2 . The forming method for a semiconductor structure according to claim 1 , wherein the substrate further comprises a peripheral region and at the time of patterning the initial conductive layer in the memory region to form a plurality of initial bit line structures, the method further comprises: patterning the initial conductive layer in the peripheral region to form peripheral gates; and after the patterning the initial conductive layer in the memory region to form a plurality of initial bit line structures, the method further comprises: forming a peripheral gate protective layer on a sidewall of each of the peripheral gates, and forming a bit line protective layer on a sidewall of each of the initial bit line structures.
3 . The forming method for a semiconductor structure according to claim 2 , wherein the etching mask is further provided with a second opening, the second opening exposes a part of the peripheral gates in the peripheral region, and at the time of patterning the initial bit line structures and the initial bit line contact layer by employing the etching mask, the method further comprises: patterning each of the peripheral gates by employing the etching mask to form two opposite peripheral sub-gates, wherein an arrangement direction of the two opposite peripheral sub-gates is an extension direction of the peripheral gates.
4 . The forming method for a semiconductor structure according to claim 2 , after the patterning the initial conductive layer in the memory region to form a plurality of initial bit line structures, further comprising: forming a peripheral mask, wherein the peripheral mask covers the dummy region, the boundary region, and the peripheral region; removing, by employing the peripheral mask, the bit line protective layer located on the substrate in the array region to expose the substrate in the array region; and removing the peripheral mask and filling an initial contact layer between the plurality of initial bit line structures.
5 . The forming method for a semiconductor structure according to claim 4 , further comprising: patterning the initial contact layer to form node contact layers arranged at intervals in the first direction, wherein a node spacing groove exists between adjacent ones of the node contact layers; and filling the node spacing groove with a node isolation structure.
6 . The forming method for a semiconductor structure according to claim 5 , further comprising: removing a part of the node contact layers to form node contact structures; forming plug grooves in the boundary region and the peripheral region; and forming contact pad structures located above the node contact structures, a bit line pad contact structure located in the plug groove in the boundary region, and a peripheral contact structure located in the plug groove in the peripheral region.
7 . The forming method for a semiconductor structure according to claim 1 , wherein the plurality of initial bit line structures comprise first initial bit line structures and second initial bit line structures arranged alternately in the second direction; and the dummy region comprises a first dummy region and a second dummy region respectively located on two sides of the array region in the first direction; the first openings expose a part of the first initial bit line structures located in the first dummy region, and the first openings further expose a part of the second initial bit line structures located in the second dummy region; and the plurality of bit line structures extend in the first direction and are arranged at intervals in the second direction, the plurality of bit line structures comprise first bit lines and second bit lines arranged alternately in the second direction, the first bit lines are formed by a part of the first initial bit line structures located in the array region and the second dummy region, and the second bit lines are formed by a part of the second initial bit line structures located in the array region and the first dummy region.
8 . A semiconductor structure, comprising: a substrate, the substrate comprising a memory region and a boundary region sequentially adjacent to each other, and the memory region comprising an array region and a dummy region; a plurality of bit line structures located in the memory region, the plurality of bit line structures extending in a first direction and being arranged at intervals in a second direction, and the plurality of bit line structures comprising first bit lines and second bit lines arranged alternately in the second direction; a plurality of bit line contact pads located in the boundary region, the plurality of bit line contact pads being arranged at intervals in the second direction, and the second bit lines extending to the dummy region and being connected to the bit line contact pads in a one-to-one correspondence; and bit line isolation structures located in the dummy region and the boundary region, each of the bit line isolation structures comprising a first isolation portion located between the second bit lines and a second isolation portion located between the bit line contact pads, and a first width of the first isolation portion being greater than a second width of the second isolation portion.
9 . The semiconductor structure according to claim 8 , wherein the dummy region comprises a first dummy region and a second dummy region respectively located on two sides of the array region in the first direction, and the boundary region comprises a first boundary region and a second boundary region respectively located on two sides of the memory region in the first direction; the first bit lines extend to the second dummy region and are connected to the bit line contact pads located in the second boundary region in a one-to-one correspondence; and the second bit lines extend to the first dummy region and are connected to the bit line contact pads located in the first boundary region in a one-to-one correspondence.
10 . The semiconductor structure according to claim 8 , wherein the substrate further comprises a peripheral region and the semiconductor structure further comprises: two opposite peripheral sub-gates located in the peripheral region; a gate isolation structure located between opposite first sidewalls of the two opposite peripheral sub-gates, wherein the gate isolation structure has a same material as the bit line isolation structures; and a peripheral gate protective layer located on second sidewalls of the two opposite peripheral sub-gates, wherein the second sidewalls are adjacent to the first sidewalls, and a material of the peripheral gate protective layer is different from the material of the gate isolation structure.
11 . The semiconductor structure according to claim 8 , wherein the first width of the first isolation portion is equal to a spacing between adjacent ones of the second bit lines.
12 . The semiconductor structure according to claim 8 , wherein the second width of the second isolation portion is equal to a width of a bit line of each of the bit line structures.
13 . The semiconductor structure according to claim 8 , further comprising: a plurality of node contact structures located in the array region, wherein the plurality of node contact structures are arranged in an array in the first direction and the second direction.
14 . The semiconductor structure according to claim 13 , wherein the node contact structures located in the array region are embedded in the substrate and in contact with array active regions in the substrate; and the second isolation portion located in the dummy region is located on the substrate and is flush with a top surface of the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Patent Application No. PCT/CN2025/091384 filed on April 27, 2025, which claims priority to Chinese Patent Application No. 202411559807.9 filed on November 4, 2024. The disclosures of the above-referenced application are hereby incorporated by reference in their entirety. BACKGROUND With development of the electronic industry and a requirement of a user, an electronic device is designed to be small in size and high in performance. In this case, a memory employed in the electronic device is also required to be highly integrated and have high performance. To improve the degree of integration of the memory, the pattern line width of a semiconductor structure gradually decreases. However, an increase in the integration density of the semiconductor structure may cause a deterioration in the reliability of the semiconductor structure. In addition, with high development of the electronic industry, a demand for a highly reliable semiconductor structure is increasing. Therefore, many studies are underway to achieve the highly reliable semiconductor structure. SUMMARY Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor structure and a forming method therefor. According to a first aspect of the embodiments of the present disclosure, a forming method for a semiconductor structure is provided, including the following: A substrate is provided. The substrate includes a memory region and a boundary region sequentially adjacent to each other, and the memory region includes an array region and a dummy region. An initial conductive layer is formed on the substrate. The initial conductive layer in the memory region is patterned to form multiple initial bit line structures and the initial conductive layer in the boundary region is retained to form an initial bit line contact layer. The multiple initial bit line structures extend in a first direction and are arranged at intervals in a second direction. An etching mask provided with multiple first openings is formed. The multiple first openings expose a part of the initial bit line structures in the dummy region and a part of the initial bit line contact layer in the boundary region. The initial bit line structures and the initial bit line contact layer are patterned by employing the etching mask to form multiple bit line structures and multiple bit line contact pads. Bit line isolation structures are formed. Each of the bit line isolation structures includes a first isolation portion located between the bit line structures and a second isolation portion located between the bit line contact pads, and a first width of the first isolation portion is greater than a second width of the second isolation portion. According to a second aspect of the embodiments of the present disclosure, a semiconductor structure is provided, including the following: a substrate, where the substrate includes a memory region and a boundary region sequentially adjacent to each other, and the memory region includes an array region and a dummy region; multiple bit line structures located in the memory region, where the multiple bit line structures extend in a first direction and are arranged at intervals in a second direction, and the multiple bit line structures include first bit lines and second bit lines arranged alternately in the second direction; multiple bit line contact pads located in the boundary region, where the multiple bit line contact pads are arranged at intervals in the second direction, and the second bit lines extend to the dummy region and are connected to the bit line contact pads in a one-to-one correspondence; and bit line isolation structures located in the dummy region and the boundary region, where each of the bit line isolation structures includes a first isolation portion located between the second bit lines and a second isolation portion located between the bit line contact pads, and a first width of the first isolation portion is greater than a second width of the second isolation portion. BRIEF DESCRIPTION OF DRAWINGS To describe the technical solutions in the embodiments of the present disclosure or the conventional technologies more clearly, the following briefly describes the accompanying drawings required for describing the embodiments or the conventional technologies. Clearly, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other accompanying drawings from these accompanying drawings without creative efforts. FIG. 1 is a flowchart of a forming method for a semiconductor structure according to an example embodiment; FIG. 2A to FIG. 11C are schematic top views and schematic cross-sectional views of a semiconductor structure in a forming procedure according to an embodiment of the present dis