US-20260129824-A1 - SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREFOR

US20260129824A1US 20260129824 A1US20260129824 A1US 20260129824A1US-20260129824-A1

Abstract

A semiconductor structure and a fabrication method therefor are provided. The semiconductor structure includes: multiple stacked substructures located on a substrate; word line layers; a first word line isolation structure; and a second word line isolation structure, where the second word line isolation structure includes a first isolation portion, a second isolation portion, and a third isolation portion that are sequentially connected, the first isolation portion and the third isolation portion extend in the vertical direction, the second isolation portion extends in a second direction and connects the bottom of the first isolation portion and the bottom of the third isolation portion, and the bottom end of each of the word line layers is connected to the top of the second isolation portion. The foregoing semiconductor structure can improve the reliability of the semiconductor structure.

Inventors

Hong Wang
Guoliang WAN
Xiaojie Li

Assignees

CXMT Corporation

Dates

Publication Date: 20260507
Application Date: 20250704
Priority Date: 20241104

Claims (16)

1 . A semiconductor structure, comprising: a plurality of stacked substructures located on a substrate, the plurality of stacked substructures being arranged at intervals in a first direction, and each of the stacked substructures comprising active layers and first dielectric layers that are alternately stacked in a vertical direction; word line layers, each of the word line layers being located on a top surface of each of the stacked substructures and sidewalls thereof perpendicular to the first direction, and a bottom end of each of the word line layers being lower than a bottom surface of the stacked substructures; a first word line isolation structure, the first word line isolation structure being located between the stacked substructures; and a second word line isolation structure, the second word line isolation structure comprising a first isolation portion, a second isolation portion, and a third isolation portion that are sequentially connected, the first isolation portion and the third isolation portion extending in the vertical direction, the second isolation portion extending in a second direction and connecting a bottom of the first isolation portion and a bottom of the third isolation portion, and the bottom end of each of the word line layers being connected to a top of the second isolation portion.
2 . The semiconductor structure according to claim 1 , wherein the substrate comprises protrusion portions located under the stacked substructures, the second isolation portion is located between the protrusion portions, and the top surface of the second isolation portion is lower than a top surface of each of the protrusion portions.
3 . The semiconductor structure according to claim 2 , further comprising: a gate dielectric layer, wherein the gate dielectric layer covers a sidewall of each of the active layers perpendicular to the first direction; and a substrate protective layer, wherein the substrate protective layer covers sidewalls and a bottom of a groove formed between adjacent ones of the protrusion portions, and the substrate protective layer is sandwiched between the second isolation portion and the substrate; wherein a thickness of the substrate protective layer is greater than a thickness of the gate dielectric layer, and a ratio of the thickness of the substrate protective layer to a thickness of each of the first dielectric layers ranges from 0.5 to 0.6.
4 . The semiconductor structure according to claim 1 , wherein a width of the first word line isolation structure in the second direction is equal to a width of each of the word line layers in the second direction, and a width of the second word line isolation structure in the second direction is equal to a width of the each of stacked substructures in the second direction.
5 . The semiconductor structure according to claim 1 , wherein a width of the first word line isolation structure in the first direction is equal to a spacing of adjacent ones of the word line layers in the first direction, and a width of the second word line isolation structure in the first direction is equal to a spacing of adjacent ones of the stacked substructures in the first direction.
6 . The semiconductor structure according to claim 1 , wherein each of the word line layers is in an inverted U-shaped morphology in a cross section in the first direction and the vertical direction.
7 . The semiconductor structure according to claim 6 , wherein each of the word line layers comprises a first word line portion, a second word line portion, and a third word line portion that are sequentially connected, each of the first word line portion and the third word line portion is located on a sidewall of each of the stacked substructures perpendicular to the first direction, the second word line portion connects a top of the first word line portion and a top of the third word line portion, and the second word line portion is located on the top surface of each of the stacked substructures.
8 . The semiconductor structure according to claim 3 , wherein materials of the substrate protective layer and the first dielectric layers are the same, and a thickness of each of the first dielectric layers in the vertical direction is at most twice a thickness of the substrate protective layer in the vertical direction.
9 . A fabrication method for a semiconductor structure, comprising: forming a plurality of stacked substructures located on a substrate, the plurality of stacked substructures being arranged in a first direction, and each of the stacked substructures comprising active layers and first dielectric layers that are alternately stacked in a vertical direction; forming a sacrificial structure located between the stacked substructures; forming a word line material layer and a first word line isolation structure, the word line material layer being located on a top surface of each of the stacked substructures, sidewalls thereof perpendicular to the first direction, and a part of a surface of the sacrificial structure, and the first word line isolation structure being located between the stacked substructures; removing the sacrificial structure to form a communication trench; removing a part of the word line material layer exposed by the communication trench to form word line layers, each of the word line layers being located on a top surface of each of the stacked substructures and sidewalls thereof perpendicular to the first direction, and a bottom end of each of the word line layers being lower than a bottom surface of each of the stacked substructures; and forming a second word line isolation structure filling the communication trench, the second word line isolation structure comprising a first isolation portion, a second isolation portion, and a third isolation portion that are sequentially connected, the first isolation portion and the third isolation portion extending in the vertical direction, the second isolation portion extending in a second direction and connecting a bottom of the first isolation portion and a bottom of the third isolation portion, and the bottom end of each of the word line layers being connected to a top of the second isolation portion.
10 . The fabrication method according to claim 9 , wherein the forming stacked substructures located on a substrate comprises: forming stacked structures located on the substrate, wherein each of the stacked structures comprises first semiconductor layers and second semiconductor layers that are alternately stacked; removing a part of the stacked structures and the substrate to form a plurality of first through-holes and patterned stacked structures, wherein the plurality of first through-holes are arranged in the first direction and run through the stacked structures, and each of the patterned stacked structures is located between the first through-holes; removing a part of the first semiconductor layers through lateral etching along the first through-holes to form first gap trenches, wherein the first gap trenches are in communication with the plurality of first through-holes; and depositing first dielectric layers to form the stacked substructures, wherein the first dielectric layers fill the first gap trenches and cover sidewalls of the plurality of first through-holes.
11 . The fabrication method according to claim 10 , wherein the forming a sacrificial structure located between the stacked substructures comprises: forming vertical sacrificial portions filling the plurality of first through-holes; and removing a part of each of the vertical sacrificial portions to form the sacrificial structure, wherein the sacrificial structure comprises a first sacrificial portion, a second sacrificial portion, and a third sacrificial portion that are sequentially connected, the first sacrificial portion and the third sacrificial portion extend in the vertical direction, the second sacrificial portion extends in the second direction and connects a bottom of the first sacrificial portion and a bottom of the third sacrificial portion, and a top surface of the second sacrificial portion is lower than the bottom surface of each of the stacked substructures.
12 . The fabrication method according to claim 11 , wherein a word line trench is enclosed by the first sacrificial portion, the second sacrificial portion, and the third sacrificial portion; and the forming a word line material layer and a first word line isolation structure comprises: removing a part of the first dielectric layers that are located on sidewalls of the first through-holes and that are exposed by the word line trench; forming a gate dielectric layer on a sidewall of each of the active layers exposed by the word line trench; and forming the word line material layer conformally covering an inner wall of the word line trench, and filling the first word line isolation structure.
13 . The fabrication method according to claim 11 , wherein the removing the sacrificial structure comprises: performing planarization processing to expose a top surface of the first sacrificial portion and a top surface of the third sacrificial portion; and removing the first sacrificial portion, the second sacrificial portion, and the third sacrificial portion by adopting a wet etching process.
14 . The fabrication method according to claim 10 , wherein a bottom surface of each of the first through-holes is lower than a top surface of the substrate.
15 . The fabrication method according to claim 11 , wherein during forming vertical sacrificial portions filling the plurality of first through-holes, the method further comprises: forming a horizontal sacrificial portion, wherein the horizontal sacrificial portion connects top surfaces of a plurality of ones of the vertical sacrificial portions arranged at intervals in the first direction.
16 . The fabrication method according to claim 12 , wherein the substrate comprises protrusion portions located under the stacked substructures; and when a part of each of the vertical sacrificial portions and a part of the first dielectric layers are removed, a second sacrificial portion and a substrate protective layer that are located in a groove between the protrusion portions are retained; and a top surface of the second sacrificial portion is flush with a top surface of the substrate protective layer, and is lower than a top surface of each of the protrusion portions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present disclosure is a continuation of International Application No. PCT/CN2025/077782 filed on Feb. 18, 2025, which claims priority to Chinese Patent Application No. 202411571317.0 filed on Nov. 4, 2024. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety. BACKGROUND The development of dynamic random access memory (DRAM) targets performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of semiconductor device structure sizes, technical barriers encountered by existing structures become increasingly obvious. Therefore, developing more novel structures based on the existing structures is an advantageous means to break existing technical barriers. The emergence of three-dimensional dynamic random access memory (3D DRAM), in particular, 3D DRAM incorporating a multilayer horizontal cell (MHC), which usually includes multiple transistors stacked on a substrate, meets the foregoing requirements. However, in a procedure of forming a vertical wire (e.g., a word line) in the three-dimensional dynamic random access memory, due to a limitation of a dry etching process, a short circuit problem of the wire caused by a residual conductive material is prone to occur. Consequently, the reliability of the memory is reduced. SUMMARY Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor structure and a fabrication method therefor. According to a first aspect of the embodiments of the present disclosure, a semiconductor structure is provided, including: multiple stacked substructures located on the substrate, where the multiple stacked substructures are arranged at intervals in a first direction, and each of the stacked substructures includes active layers and first dielectric layers that are alternately stacked in the vertical direction; word line layers, where each of the word line layers is located on the top surface of each of the stacked substructures and sidewalls thereof perpendicular to the first direction, and the bottom end of each of the word line layers is lower than the bottom surface of each of the stacked substructures; a first word line isolation structure, where the first word line isolation structure is located between the stacked substructures; and a second word line isolation structure, where the second word line isolation structure includes a first isolation portion, a second isolation portion, and a third isolation portion that are sequentially connected, the first isolation portion and the third isolation portion extend in the vertical direction, the second isolation portion extends in a second direction and connects the bottom of the first isolation portion and the bottom of the third isolation portion, and the bottom end of each of the word line layers is connected to the top of the second isolation portion. In some embodiments, the substrate includes protrusion portions located under the stacked substructures, the second isolation portion is located between the protrusion portions, and the top surface of the second isolation portion is lower than the top surface of each of the protrusion portions. In some embodiments, the semiconductor structure further includes: a gate dielectric layer, where the gate dielectric layer covers a sidewall of each of the active layers perpendicular to the first direction; and a substrate protective layer, where the substrate protective layer covers sidewalls and the bottom of a groove formed between adjacent ones of the protrusion portions, and the substrate protective layer is sandwiched between the second isolation portion and the substrate; where the thickness of the substrate protective layer is greater than the thickness of the gate dielectric layer, and the ratio of the thickness of the substrate protective layer to the thickness of each of the first dielectric layers ranges from 0.5 to 0.6. In some embodiments, the width of the first word line isolation structure in the second direction is equal to the width of each of the word line layers in the second direction, and the width of the second word line isolation structure in the second direction is equal to the width of the each of stacked substructures in the second direction. In some embodiments, the width of the first word line isolation structure in the first direction is equal to a spacing of adjacent ones of the word line layers in the first direction, and the width of the second word line isolation structure in the first direction is equal to a spacing of adjacent ones of the stacked substructures in the first direction. In some embodiments, each of the word line layers is in an inverted U-shaped morphology in a cross section in the first direction and the vertical direction. In some embodiments, each of the word line layers comprises a first word line portion, a second word