US-20260129825-A1 - Memory Circuitry And Methods Used In Forming Memory Circuitry

Abstract

Memory circuitry comprises an integrated circuit die comprising a radially-outermost region surrounding a radially-inner region. The inner region comprises a memory-array region. The radially-outermost region comprises a lower semiconductor material, insulative material directly above the lower semiconductor material, and a stack comprising alternating tiers of different composition semiconductive materials directly above the insulative material. A conductive-wall construction is in the radially-outermost region at least partially surrounding the inner region. Other embodiments, including methods, are disclosed.

Inventors

• Pavani Vamsi Krishna NITTALA
• Yuichi Yokoyama
• Brenda Li
• Muralikrishnan Balakrishnan
• Kolya Yastrebenetsky

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20250910

Claims (20)

1. 1 . Memory circuitry comprising: an integrated circuit die comprising a radially-outermost region surrounding a radially-inner region, the radially-inner region comprising a memory-array region comprising memory cells, the radially-outermost region comprising: a lower semiconductor material; an insulative material directly above the lower semiconductor material; and a stack comprising alternating tiers of different composition semiconductive materials directly above the insulative material; and a conductive-wall construction in the radially-outermost region at least partially surrounding the radially-inner region, the conductive-wall construction extending through the stack and the insulative material to the lower semiconductor material, the conductive-wall construction comprising two laterally-outer regions of insulating material having a conductive core laterally there-between, the conductive core being directly electrically coupled to the lower semiconductor material.
2. 2 . The memory circuitry of claim 1 wherein the conductive-wall construction completely surrounds the radially-inner region.
3. 3 . The memory circuitry of claim 1 wherein the memory cells are vertically stacked in the memory-array region and individually comprise a capacitor and a horizontal transistor.
4. 4 . The memory circuitry of claim 1 wherein one of the different composition semiconductive materials comprises silicon and the other comprises a silicon-germanium alloy.
5. 5 . The memory circuitry of claim 4 wherein the silicon is at least twice as thick as the silicon-germanium alloy.
6. 6 . The memory circuitry of claim 1 wherein the lower semiconductor material comprises silicon.
7. 7 . The memory circuitry of claim 1 wherein the insulative material comprises silicon dioxide.
8. 8 . The memory circuitry of claim 1 wherein, the memory cells are vertically stacked in the memory-array region and individually comprise a capacitor and a horizontal transistor; one of the different composition semiconductive materials comprises silicon and the other comprises a silicon-germanium alloy; the lower semiconductor material comprises silicon; and the insulative material comprises silicon dioxide.
9. 9 . The memory circuitry of claim 1 wherein the two laterally-outer regions of insulating material terminate above or in the insulative material.
10. 10 . The memory circuitry of claim 1 wherein the conductive core comprises two laterally-outer regions of a first conductive material and a laterally-inner region of a second conductive material laterally there-between, the first and second conductive materials being of different compositions relative one another.
11. 11 . The memory circuitry of claim 1 comprising two of said conductive-wall construction in the radially-outermost region, the two conductive-wall constructions being laterally spaced from one another in the stack.
12. 12 . The memory circuitry of claim 11 wherein the conductive cores of the two conductive-wall constructions are directly against one another in the lower semiconductor material.
13. 13 . Memory circuitry comprising: an integrated circuit die comprising a radially-outermost region surrounding a radially-inner region; the radially-inner region comprising a memory-array region and an adjacent region horizontally adjacent the memory-array region, the memory-array region comprising vertically-alternating insulative tiers and memory-cell tiers, the memory-cell tiers comprising memory cells that individually comprise a horizontal transistor comprising a gate, the gate comprising part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier and that extend horizontally from the memory-array region into the adjacent region; the radially-outermost region comprising: a lower semiconductor material; an insulative material directly above the lower semiconductor material; and a stack comprising alternating tiers of different composition semiconductive materials directly above the insulative material; a conductive-wall construction in the radially-outermost region at least partially surrounding the radially-inner region; conductive-via constructions in the adjacent region that individually directly electrically couple to individual of the access lines; the conductive-wall construction extending through the stack and the insulative material to the lower semiconductor material, the conductive-wall construction comprising two laterally-outer regions of insulating material having conductive core material laterally there-between, the conductive core material being directly electrically coupled to the lower semiconductor material; and the conductive-via constructions individually comprising a conductive core and a radially-outer insulative lining circumferentially there-about, the conductive core being of the same conductive core material as the conductive-wall construction, the radially-outer insulative lining being of the same insulating material as the two laterally-outer regions of the conductive-wall construction.
14. 14 . The memory circuitry of claim 13 wherein the conductive core material comprises first and second conductive materials that are of different compositions relative one another.
15. 15 . The memory circuitry of claim 14 wherein, in the conductive-wall construction, the first conductive material is in two laterally-outer regions that are laterally outward of a laterally-inner region of the second conductive material; and in the conductive-via constructions, the first conductive material is in a radially-outer region that is directly against the radially-outer insulative lining and is radially outward of the second conductive material.
16. 16 . The memory circuitry of claim 15 wherein the first conductive material is titanium nitride and the second conductive material is elemental tungsten.
17. 17 . The memory circuitry of claim 16 wherein the insulating material is silicon nitride.
18. 18 . The memory circuitry of claim 13 wherein the two laterally-outer regions of insulating material terminate above or in the insulative material.
19. 19 . Memory circuitry comprising: an integrated circuit die comprising a radially-outermost region surrounding a radially-inner region; the radially-inner region comprising a memory-array region comprising memory cells that individually comprise a capacitor; the radially-outermost region comprising: a lower semiconductor material; an insulative material directly above the lower semiconductor material; and a stack comprising alternating tiers of different composition semiconductive materials directly above the insulative material; a conductive-wall construction in the radially-outermost region at least partially surrounding the radially-inner region; the capacitor comprising a conductive storage node electrode, a conductive cell plate electrode comprising conductive material, and a capacitor insulator comprising insulator material there-between; and the conductive-wall construction extending through the stack and the insulative material to the lower semiconductor material, the conductive-wall construction comprising two laterally-outer regions of insulating material having conductive core material laterally there-between, the conductive core material being directly electrically coupled to the lower semiconductor material, the conductive core material being of the same conductive material as the cell plate electrode.
20. 20 . The memory circuitry of claim 19 wherein the conductive material comprises conductively-doped semiconductive material.

Description

TECHNICAL FIELD Embodiments disclosed herein pertain to memory circuitry and to methods used in forming memory circuitry. BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. Memory cells may be arranged or arrayed in several manners including essentially horizontally in a single plane or alternately, for example, in a vertical stack (e.g., along a z direction) comprising a three-dimensional (3D) memory-array region having horizontal tiers in which individual memory cells are received (e.g., arrayed in x and y directions). The stack in the 3D memory-array region comprises vertically-alternating insulative tiers and conductive tiers (e.g., as part of memory-cell tiers) that extend into a stair-step region. The stair-step region includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of conductive lines of individual of the conductive tiers to which vertical conductive vias can contact to provide electrical access to/from those conductive lines. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic schematic of a DRAM memory array and peripheral circuitry in accordance with the prior art and in accordance with an embodiment of the invention. FIG. 2 is an enlargement of a portion of FIG. 1. FIGS. 3-41 are diagrammatic sequential sectional and/or enlarged views of a construction, or portions thereof or alternate and/or additional embodiments, in process in accordance with some embodiments of the invention. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Embodiments of the invention encompass memory circuitry (e.g., DRAM) regardless of orientation (e.g., either horizontal or vertical). In some ideal embodiments, the memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers, with memory cells in the memory-cell tiers individually comprising a capacitor and a horizontally-oriented transistor. Embodiments of the invention also encompass methods used in forming memory circuitry. Example embodiments are described with reference to FIGS. 1-41. One example prior art schematic diagram of DRAM circuitry, and in accordance with an embodiment of the invention, is shown in FIGS. 1 and 2. FIG. 2 shows example memory cells MC individually comprising a transistor T and a capacitor C. One electrode of capacitor C is directly electrically coupled to a suitable potential (e.g., ground) and the other capacitor electrode is contacted with or comprises one of the source/drain regions of transistor T. The other source/drain region of transistor T is directly electrically coupled with a digitline/sense line 130 or 131 (also individually designated as DL). The gate of transistor T is directly electrically coupled with (e.g., comprises part thereof) a wordline/access line WL. FIG. 1 shows digitlines 130 and 131 extending from one of opposite sides 100 and 200 of a memory array area 10 into a peripheral circuitry area 113 that is aside memory array area 10. Digitlines 130 and 131 individually directly electrically couple with a sense amp SA on opposite sides 100 and 200 of array area 10 within peripheral circuitry area 113. Sense amps SA could be on only one side or all directly above or directly below memory array area 10. Non-schematic structure embodiments as shown herein in FIG. 3+ have the wordlines/access lines running horizontally and the digitlines/sense lines running vertically. Referring to FIGS. 3-5, an example semiconductor wafer 6 comprises a base substrate 11 and which may comprise any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrical