US-20260129826-A1 - SUBSTRATE ISOLATION IN A THREE DIMENSIONAL (3D) MEMORY ARRAY

Abstract

Systems, methods, and apparatus are provided for substrate isolation in a three-dimensional (3D) memory array. The 3D array of vertically stacked memory cells can include a substrate, a horizontal dielectric material formed on the substrate, a 3d array of vertically stacked memory cells formed on the dielectric material, wherein the vertically stacked memory cells have horizontally oriented access devices and horizontally oriented storage nodes, and vertical sense line material formed adjacent to, and in contact with, the horizontally oriented access device. The vertical sense line material is formed on the horizontal dielectric material such that a bottom portion of the vertical sense line material extends below a bottom surface of the 3D array of vertically stacked memory cells and into the horizontal dielectric material.

Inventors

• Alyssa N. Scarbrough
• Frank Speetjens
• Jordan D. Greenlee

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20251028

Claims (20)

1. 1 . A method for forming three dimensional (3D) arrays of vertically stacked memory cells, having horizontally oriented access devices and storage nodes, comprising: forming a vertical stack comprising alternating layers of a first material and a second material on a substrate; forming first vertical openings through the vertical stack and into the substrate to form sidewalls of the vertical stack; forming a doped silicon (Si) material on a substrate; forming a passivation material on the sidewalls of the vertical stack and a bottom portion of each first vertical opening; removing the doped silicon material to form a horizontal opening; depositing a dielectric material in the first vertical openings and the horizontal opening; removing a first portion of the dielectric material to reform a portion of the first vertical openings and expose the sidewalls of the vertical stack; forming horizontal access devices in the vertical stack; forming a vertical sense line in the reformed portion of each of the first vertical openings; forming a second vertical opening through the vertical stack and into the dielectric material; forming horizontal storage nodes in the vertical stack and adjacent the second vertical opening.
2. 2 . The method of claim 1 , further comprising epitaxially growing the doped Si material on the substrate.
3. 3 . The method of claim 1 , wherein the doped Si material is a doped silicon germanium (SiGe) material.
4. 4 . The method of claim 1 , further comprising epitaxially growing the passivation material on the sidewalls of the vertical stack and the bottom portion of each first vertical opening.
5. 5 . The method of claim 1 , wherein the passivation material is an oxide material.
6. 6 . The method of claim 1 , wherein the passivation material is a tungsten (W) material.
7. 7 . The method of claim 1 , wherein the first material is a silicon germanium (SiGe) material.
8. 8 . The method of claim 1 , wherein the second material is a Si material.
9. 9 . A method for forming three dimensional (3D) arrays of vertically stacked memory cells, having horizontally oriented access devices and storage nodes, comprising: depositing alternating layers of silicon germanium (SiGe) material and Si material to form a vertical stack on a substrate; depositing a mask material over the vertical stack; performing a first etch to form first vertical openings through the vertical stack and into the substrate to from sidewalls of the vertical stack; doping a layer of silicon (Si) material on the substrate to form doped Si material on the substrate; epitaxially growing passivation material on the sidewalls of the vertical stack and a bottom portion of the first vertical openings; performing a second etch to remove the doped Si material on the substrate to create a horizontal opening; depositing a dielectric material in the first vertical openings and the horizontal opening; performing a third etch to remove portions of the dielectric material to reform portions of the first vertical openings and expose the sidewalls of the vertical stack; forming horizontal access devices in the vertical stack; depositing a sense line in the portions of the first vertical openings; performing a fourth etch to form second vertical openings through the vertical stack and into the dielectric material; and forming horizontal storage nodes in the vertical stack adjacent the second vertical openings.
10. 10 . The method of claim 9 , further comprising depositing a fill material to fill the third vertical openings.
11. 11 . The method of claim 9 , further comprising forming anchors between parallel vertical stacks.
12. 12 . The method of claim 9 , wherein the first etch, the second etch, the third etch, and the fourth etch are each wet etches.
13. 13 . The method of claim 9 , wherein the third etch removes the passivation material from the sidewalls of the vertical stack.
14. 14 . The method of claim 9 , further comprising depositing the dielectric material over the substrate and the passivation material formed on the bottom portion of the first vertical openings.
15. 15 . The method of claim 9 , further comprising doping the doped Si material with a boron (B) material.
16. 16 . The method of claim 9 , further comprising doping the doped Si material with a phosphorous (P) material.
17. 17 . The method of claim 9 , further comprising doping the doped Si material with a carbon (C) material.
18. 18 . A memory device comprising: a substrate; a horizontal dielectric material formed on the substrate; a three dimensional (3D) array of vertically stacked memory cells formed on the dielectric material, the vertically stacked memory cells having horizontally oriented access devices and horizontally oriented storage nodes; and vertical sense line material formed adjacent to, and in contact with, the horizontally oriented access devices, wherein the vertical sense line material is formed on the horizontal dielectric material such that a bottom portion of the vertical sense line material extends below a bottom surface of the 3D array of vertically stacked memory cells and into the horizontal dielectric material.
19. 19 . The memory device of claim 18 , wherein a vertical top electrode adjacent the horizontally oriented storage nodes is shared between storage nodes of adjacent arrays to form a shared electrode in the 3D array of vertically stacked memory cells.
20. 20 . The memory device of claim 19 , wherein the shared electrode for storage nodes to the 3D array of vertically stacked memory cells extends below a bottom surface of the 3D array of vertically stacked memory cells a different depth into the horizontal dielectric material than a bottom surface of the vertical sense line material.

Description

PRIORITY INFORMATION This application claims the benefit of U.S. Provisional Application No. 63/715,883, filed on Nov. 4, 2024, the contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates generally to memory devices, and more particularly, to substrate isolation in a 3D memory array. BACKGROUND Memory is often implemented in electronic systems, such as computers, cell phones, hand-held devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM). Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, nitride read only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random-access memory), cross-point memory, ferroelectric random-access memory (FeRAM), or the like. As design rules shrink, less semiconductor space is available to fabricate memory, including DRAM arrays. A respective memory cell for DRAM may include an access device, e.g., transistor, having a first and a second source/drain region separated by a channel region. A gate may oppose the channel region and be separated therefrom by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the DRAM memory cell. A DRAM memory cell can include a storage node, such as a capacitor cell, coupled by the access device to a sense line, such as a digit line. The access device can be activated (e.g., to select the cell) by an access line coupled to the access device. The capacitor can store a charge corresponding to a data value of a respective memory cell (e.g., a logic “1” or “0”). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic illustration of an array of memory cells in a vertical three dimensional (3D) memory in accordance with a number of embodiments of the present disclosure. FIG. 1B is a perspective view illustrating a portion of a horizontal access devices in vertical three dimensional (3D) memory in accordance with a number of embodiments of the present disclosure. FIG. 2 illustrates a portion of a horizontal access device in vertical three dimensional (3D) memory in accordance with a number of embodiments of the present disclosure. FIG. 3 is a schematic illustration of a vertical three dimensional memory in accordance with a number of embodiments of the present disclosure. FIG. 4 is a perspective view illustrating horizontal access devices in accordance with a number of embodiments of the present disclosure. FIG. 5 is a cross-sectional view of a vertical stack in vertical three dimensional (3D) memory in accordance with a number of embodiments of the present disclosure. FIGS. 6A to 6I illustrate an example method, at one stage of a semiconductor fabrication process, for substrate isolation in a 3D memory array, in accordance with a number of embodiments of the present disclosure. FIG. 7 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure. DETAILED DESCRIPTION Embodiments of the present disclosure describe substrate isolation in a three dimensional (3D) memory array. A memory device can include a substrate, a horizontal dielectric material formed on the substrate, a 3D array of vertically stacked memory cells formed on the dielectric material, wherein the vertically stacked memory cells have horizontally oriented access devices and horizontally oriented storage nodes. The memory device can also include a vertical sense line material formed adjacent to, and in contact with, the horizontally oriented access devices, wherein the vertical sense line material is formed on the horizontal dielectric material such that a bottom portion of the vertical sense line material extends below a bottom surface of, the 3D array of vertically stacked memory cells into the horizontal dielectric material. In some previous approaches, substrate isolation in 3D memory arrays of vertically stacked memory cells does not scale with the number of layers of memory in a memory stack. The more layers of memory that a memory stack includes, the more difficult it is to stop an etch on a bottom-most silicon (Si) layer in a memory stack. Failing to stop an etch on a bottom-most Si layer can result in the performance of the material deposited in the opening formed by the etch not functioning as intended to being formed to unintended dimensions. Embodiments described herein, however, can an etch more consistently stopping in the intended layer of material. This can be achieved by replacing a bottom layer of a Si material or SiGe material with a dielectric material. By repla