US-20260129827-A1 - WORD LINE CONTACT FOR 3D MEMORY

Abstract

Described are memory devices having an array region and a contact region adjacent the array region. The array region includes a cell transistor and a cell capacitor. The contact region includes a plurality of word line contacts extending in a first direction and a second plurality of word line contacts extending in a second direction. The memory stack comprises a plurality of conductor layers and a corresponding plurality of dielectric layers alternatingly arranged in a plurality of stacked pairs. Methods of forming a memory device are described.

Inventors

• Chang Seok Kang
• Tomohiko Kitajima
• Raghuveer Satya Makala

Assignees

• APPLIED MATERIALS, INC.

Dates

Publication Date

20260507

Application Date

20251029

Claims (20)

1. 1 . A memory device comprising: a plurality of stacked word lines coupled to a plurality of stacked memory cells, the plurality of stacked word lines comprising a first word line and a second word line; a first word line contact in contact with the first word line and extending in a first direction from the first word line; and a second word line contact in contact with the second word line and extending in a second direction from the second word line, wherein the second direction is opposite to the first direction.
2. 2 . The memory device of claim 1 , wherein the plurality of stacked word lines comprises a third word line and a fourth word line, and the memory device comprises: a third word line contact contacting the third word line and extending in the first direction from the third word line; and a fourth word line contact contacting the fourth word line and extending in the second direction from the fourth word line.
3. 3 . The memory device of claim 2 , wherein first word line contact has a height that is greater than a height of the third word line contact, and the second word line contact has a height that is greater than a height of the fourth word line contact.
4. 4 . A memory device comprising: a memory stack comprising a plurality of conductor layers and semiconductor layers and a corresponding plurality of dielectric layers alternatingly arranged in a plurality of stacked pairs, the memory stack having a first direction and a second direction; at least two first contact regions extending in the first direction; and at least two second contact regions extending in the second direction.
5. 5 . The memory device of claim 4 , wherein the plurality of conductor layers comprises a one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or nitrides thereof.
6. 6 . The memory device of claim 4 , wherein the plurality of semiconductor layers comprises one or more of silicon (Si), silicon germanium (SiGe), or germanium (Ge) and wherein the plurality of dielectric layers comprises one or more of silicon oxide (SiOx), silicon nitride (SIN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN).
7. 7 . The memory device of claim 4 , wherein the first contact regions and the second contact regions independently comprise one or more of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).
8. 8 . A memory device comprising: an array region on a substrate, the array region including a cell transistor and a cell capacitor; and a contact region having a first direction and a second direction adjacent the array region on the substrate, the contact region comprising: a plurality of conductor layers and semiconductor layers and a corresponding plurality of dielectric layers alternatingly arranged in a plurality of stacked pairs, at least two first contact regions extending in the first direction, and at least two second contact regions extending in the second direction.
9. 9 . The memory device of claim 8 , wherein the plurality of conductor layers comprises a one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or nitrides thereof.
10. 10 . The memory device of claim 8 , wherein the plurality of semiconductor layers comprises one or more of silicon (Si), silicon germanium (SiGe), or germanium (Ge) and wherein the plurality of dielectric layers comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN).
11. 11 . The memory device of claim 8 , wherein the first contact regions and the second contact regions independently comprises one or more of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).
12. 12 . The memory device of claim 8 , further comprising a peri substrate electrically connected with the first contact regions and the second contact regions by a through hole via.
13. 13 . The memory device of claim 8 , wherein the memory device is a 3D DRAM device.
14. 14 . A method of manufacturing a memory device, the method comprising: forming a memory stack on a substrate, the memory stack comprising a plurality of conductor layers and semiconductor layers and a corresponding plurality of dielectric layers alternatingly arranged in a plurality of stacked pairs, the memory stack having a first direction and a second direction; patterning the memory stack in the first direction to form a plurality of first contact openings extending in the first direction; patterning the memory stack in the second direction to form a plurality of second contact openings extending in the second direction; and depositing a conductive material in each of the plurality of first contact openings and in the plurality of second contact openings to form a plurality of first contacts and a plurality of second contacts, the plurality of first contacts extending along the first direction and the plurality of second contacts extending along the second direction.
15. 15 . The method of claim 14 , wherein the plurality of conductor layers comprise a one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or nitrides thereof.
16. 16 . The method of claim 14 , wherein the plurality of semiconductor layers comprises one or more of silicon (Si), silicon germanium (SiGe), or germanium (Ge) and wherein the plurality of dielectric layers comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN).
17. 17 . The method of claim 14 , wherein the plurality of first contacts and the plurality of second contacts independently comprises one or more of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).
18. 18 . The method of claim 14 , further comprising forming a through hole via to electrically connect with the plurality of first contacts and the plurality of second contacts to a peri substrate.
19. 19 . The method of claim 14 , wherein the memory device is a 3D DRAM device.
20. 20 . A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform operations of the method of claim 14 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/716,789, filed Nov. 6, 2024, the entire disclosure of which is hereby incorporated by reference herein. TECHNICAL FIELD Embodiments of the present disclosure pertain to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the disclosure provide a three-dimensional (3D) dynamic random-access memory cell. BACKGROUND Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. There are two major types of random-access memory cells, dynamic and static, which are well-suited for use in electronic devices. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short periods of time. Static random-access memories (SRAM) are so named because they do not require periodic refreshing. DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor. The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with nonarray devices. The formation of a low resistance contact between the active area and the 3D DRAM bottom electrode is essential for performance of the device. DRAM is composed of hundreds of sub-blocks. For each sub-block, word lines (WL) and bit lines (BL) are connected with controlling circuits. Multiple cells are stacked in a 3D DRAM. Every word line of each stack should have a contact to connect the word line with controlling circuits in a sub-array. The same number of contacts are necessary as the number of word lines (WL) stacked. Word line contact (WLC) area, therefore, occupies a significant portion of total chip area. The reduction in word line contact (WLC) area is critical to decrease chip area. There is a need in the art, therefore, for memory devices and methods of forming memory devices that have a reduced chip area. SUMMARY One or more embodiments of the disclosure are directed to a memory device. In one or more embodiments, a memory device comprises: a plurality of stacked word lines coupled to a plurality of stacked memory cells, the plurality of stacked word lines comprising a first word line and a second word line; a first word line contact in contact with the first word line and extending in a first direction from the first word line; and a second word line contact in contact with the second word line and extending in a second direction from the second word line, wherein the second direction is opposite to the first direction. One or more embodiments of the disclosure are directed to a memory device. In one or more embodiments, a memory device comprises: a memory stack comprising a plurality of conductor layers and semiconductor layers and a corresponding plurality of dielectric layers alternatingly arranged in a plurality of stacked pairs, the memory stack having a first direction and a second direction; at least two first contact regions extending in the first direction; and at least two second contact regions extending in the second direction. Additional embodiments of the disclosure are directed to a memory device. In one or more embodiments, a memory device comprises: an array region on a substrate, the array region including a cell transistor and a cell capacitor; and a contact region having a first direction and a second direction adjacent the array region on the substrate, the contact region comprising a plurality of conductor layers and semiconductor layers and a corresponding plurality of dielectric layers alternatingly arranged in a plurality of stacked pairs, at least two first contact regions extending in the first direction, and at least two second contact regions extending in the second direction. Further embodiments of the disclosure are directed to methods of forming a memory device. In on