US-20260129828-A1 - SEMICONDUCTOR MEMORY DEVICE

US20260129828A1US 20260129828 A1US20260129828 A1US 20260129828A1US-20260129828-A1

Abstract

A semiconductor memory device and method for making the same. The semiconductor memory device includes an active layer spaced apart from a substrate, extending in a direction parallel to the substrate, and including a channel; a bit line extending in a vertical direction to the substrate and contacting a first end portion of the active layer; a capacitor contacting a second end portion of the active layer; a word line including a high work function electrode adjacent to the bit line and a low work function electrode adjacent to the capacitor; a first gate dielectric layer disposed between the low work function electrode and the active layer; and a second gate dielectric layer disposed between the high work function electrode and the active layer, the second gate dielectric layer being thinner than the first gate dielectric layer.

Inventors

Seung Hwan Kim

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20260105
Priority Date: 20210610

Claims (13)

1 . A method for fabricating a semiconductor memory device, the method comprising: forming a stack body of a first inter-level dielectric layer, a first sacrificial layer, a semiconductor layer, a second sacrificial layer, and a second inter-level dielectric layer which are sequentially stacked; forming a first opening penetrating the stack body; forming recesses by removing the first sacrificial layer and the second sacrificial layer through the first opening; thinning the semiconductor layer exposed by the recesses; forming a first gate dielectric layer on the thinned semiconductor layer; forming a low work function electrode on the first gate dielectric layer; forming a second gate dielectric layer by thinning a portion of the first gate dielectric layer; and forming a high work function electrode on the second gate dielectric layer, the high work function electrode contacting the low work function electrode.
2 . The method of claim 1 , wherein the low work function electrode includes an N-type doped polysilicon.
3 . The method of claim 1 , wherein the high work function electrode includes a metal-base material.
4 . The method of claim 1 , wherein the high work function electrode includes titanium nitride, tungsten, or a stack of titanium nitride and tungsten.
5 . The method of claim 1 , wherein the low work function electrode has a lower work function than a mid-gap work function of silicon, and the high work function electrode has a higher work function than the mid-gap work function of silicon.
6 . The method of claim 1 , wherein the semiconductor layer comprises a channel, a source region, and a drain region.
7 . The method of claim 6 , wherein the channel is arranged between the source region and the drain region.
8 . The method of claim 6 , wherein the low work function electrode is arranged over or under a part of the drain region.
9 . The method of claim 6 , wherein the high work function electrode is arranged over or under the channel and a part of the source region.
10 . The method of claim 6 , further comprising: forming a bit line electrically coupled to the source region of the semiconductor layer; and forming a capacitor electrically coupled to the drain region of the semiconductor layer.
11 . The method of claim 10 , further comprising: forming a bit line contact node arranged between the bit line and the source region; and forming a storage contact node between the capacitor and the drain region.
12 . The method of claim 1 , wherein the semiconductor layer includes at least one of a semiconductor material or an oxide semiconductor material.
13 . The method of claim 1 , wherein the semiconductor layer includes at least one of polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. Patent Application Serial No. 17/536,872 filed on Nov 29, 2021, which claims priority to Korean Patent Application No. 10-2021-0075555, filed on June 10, 2021, which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Various embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device including a three-dimensional memory cell. 2. Description of the Related Art Integration degree of two-dimensional semiconductor memory devices is mainly determined by the area occupied by unit memory cells. Thus, the integration degree is mainly affected by the level of a fine-pattern fabrication technology. The integration degree of two-dimensional semiconductor memory devices is still increasing, but the increase is limited because fabricating finer patterns requires highly expensive tools. Accordingly, three-dimensional (3D) semiconductor memory devices having three-dimensionally arranged memory cells are being suggested. SUMMARY Various embodiments of the present invention provide semiconductor memory device(s) including highly integrated memory cells. In accordance with one embodiment of the present invention, a semiconductor memory device may comprise: an active layer spaced apart from a substrate, extending in a direction parallel to the substrate, and including a channel; a bit line extending in a vertical direction to the substrate and contacting a first end portion of the active layer; a capacitor contacting a second end portion of the active layer; a word line including a high work function electrode which is adjacent to the bit line and a low work function electrode which is adjacent to the capacitor, the low work function electrode having a lower work function than the high work function electrode; a first gate dielectric layer disposed between the low work function electrode and the active layer; and a second gate dielectric layer disposed between the high work function electrode and the active layer, the second gate dielectric layer being thinner than the first gate dielectric layer. In accordance with another embodiment of the present invention, a method for fabricating a semiconductor memory device may comprise: forming a stack body of a first inter-level dielectric layer, a first sacrificial layer, a semiconductor layer, a second sacrificial layer, and a second inter-level dielectric layer which are sequentially stacked; forming a first opening penetrating the stack body; forming recesses by removing the first sacrificial layer and the second sacrificial layer through the first opening; thinning the semiconductor layer exposed by the recesses; forming a first gate dielectric layer on the thinned semiconductor layer; forming a low work function electrode on the first gate dielectric layer; forming a second gate dielectric layer by thinning a portion of the first gate dielectric layer; and forming a high work function electrode on the second gate dielectric layer, the high work function electrode contacting the low work function electrode. In one embodiment, the present invention may improve the gate induced drain leakage (GIDL) by forming a thick gate dielectric layer between the low work function electrode and the active layer. In one embodiment, the present invention may increase the operating current IOP by forming a thin gate dielectric layer between the high work function electrode and the active layer. In one embodiment, the present invention may realize low power consumption while securing refresh characteristics of the memory cell because the word line has a dual work function electrode structure including a low work function electrode and a high work function electrode. In one embodiment, the present invention may realize the high integration of memory cells including a thin-body channel by forming a double word line having a dual work function electrode structure. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic perspective view illustrating a memory cell of a semiconductor memory device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating the memory cell of FIG. 1. FIG. 3 is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a vertical memory cell array MCA_C of FIG. 3. FIG. 5 is a cross-sectional view illustrating edge portions of word lines. FIG. 6 is a modified example of FIG. 5 illustrating a semiconductor memory device according to another embodiment of the present invention. FIG. 7 is a schematic perspective view illustrating a semiconductor memory device according to another embodiment of the present invention. FIGS. 8A to 8I are diagrams illustrating a method for fabricating a double word line according to one embodiment of the present invention.