US-20260129829-A1 - VERTICAL THREE-DIMENSIONAL MEMORY WITH VERTICAL CHANNEL

US20260129829A1US 20260129829 A1US20260129829 A1US 20260129829A1US-20260129829-A1

Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having vertically oriented access devices having a first source/drain region and a second source drain region vertically separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the first source/drain region and horizontally oriented digit lines coupled to the second source/drain regions.

Inventors

Kamal M. Karda
Haitao Liu
Litao YANG

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20260106

Claims (20)

1 . A memory device, comprising: an array of stacked memory cells, the array, comprising: a plurality of vertically oriented access devices having respective first source/drain regions and second source/drain regions separated by a vertical channel region; a first vertically oriented access line separated from the vertical channel regions of the plurality of vertically oriented access devices by a gate dielectric; a plurality of horizontally oriented storage nodes electrically coupled to the respective first source/drain regions of the plurality of vertically oriented access devices, wherein the plurality of horizontally oriented storage nodes are respectively vertically adjacent to the plurality of vertically oriented access devices; and a plurality of digit lines electrically coupled to the respective second source/drain regions of the plurality of vertically oriented access devices.
2 . The memory device of claim 1 , further comprising a second vertically oriented access line separated, by the gate dielectric, from an opposite side of the vertical channel regions of the plurality of vertically oriented access devices.
3 . The memory device of claim 1 , wherein a horizontal width of the vertical channel region is greater than a horizontal width of the first vertically oriented access line.
4 . The memory device of claim 1 , wherein a horizontal width of the vertical channel region is less than a horizontal width of the first vertically oriented access line.
5 . The memory device of claim 1 , wherein a horizontal width of the vertical channel region is equal to a horizontal width of the first vertically oriented access line.
6 . The memory device of claim 1 , wherein the plurality of horizontally oriented storage nodes include a respective bottom electrode, a respective insulator material, and a respective top electrode.
7 . The memory device of claim 6 , wherein the respective top electrodes of the plurality of horizontally oriented storage nodes are formed of a common material.
8 . The memory device of claim 1 , wherein the vertical channel region comprises a first channel material located between instances of a second channel material in the horizontal direction, wherein the first channel material is different than the second channel material.
9 . The memory device of claim 8 , wherein the first channel material is an oxide material.
10 . The memory device of claim 9 , wherein the first channel material is a yttrium oxide material.
11 . A method for forming an array of vertically stacked memory cells having respective vertically oriented access devices, the method, comprising: forming layers of a first dielectric material, a second dielectric material, a first source/drain material, a channel material, a second source/drain material, and a third dielectric material to form a vertical stack comprising a number of tiers; forming a first vertical opening to expose first sidewalls in the vertical stack; removing a portion of the second dielectric material to form a first horizontal opening from the first vertical opening; forming a bottom electrode material, an insulator material, and a top electrode material in the first horizontal opening to form a horizontally oriented storage node, wherein the bottom electrode material is adjacent to the first source/drain material.
12 . The method of claim 11 , further comprising: forming a second vertical opening to expose second sidewalls in the vertical stack; removing portions of the third dielectric material to form a second horizontal opening from the second vertical opening; and forming a metal in the second horizontal opening to form a horizontally oriented digit line, wherein the metal contacts the second source/drain material.
13 . The method of claim 12 , wherein the metal is vertically adjacent to the second source/drain material.
14 . The method of claim 11 , further comprising: removing first portions of the first source/drain material, the channel material; and the second source/drain material to form a second horizontal opening; depositing a first constraining dielectric material in the second horizontal opening.
15 . The method of claim 14 , further comprising: removing second portions of the first source/drain material, the channel material; the second source/drain material to form a fourth horizontal opening; and depositing a second constraining dielectric material in the fourth horizontal opening.
16 . The method of claim 11 , further comprising: forming a second vertical opening to expose second sidewalls in the vertical stack; forming a gate dielectric on the second sidewalls; and depositing a conductive material in the second vertical opening and on the gate dielectric to form a vertical access line.
17 . A method for forming an array of vertically stacked memory cells having respective vertically oriented access devices, the method comprising: forming a first dielectric material, a second dielectric material, a first source/drain material, a channel material, a second source/drain material, and a third dielectric material in repeating iterations to form a vertical stack; forming a first vertical opening in the vertical stack thereby exposing first vertical sidewalls; forming, through the first vertical opening, a first horizontal opening by removing first portions of the first source/drain material, first portions of the channel material, and first portions of the second source/drain material; forming a fourth dielectric material in the first horizonal opening; forming, through the first vertical opening, a second horizontal opening by removing portions of the second dielectric material; forming a bottom electrode material, an insulator material, and a top electrode material in the first horizontal opening to form a horizontally oriented storage node, wherein the bottom electrode material is vertically adjacent to the first source/drain material.
18 . The method of claim 17 , further comprising: forming a second vertical opening in the vertical stack thereby exposing second vertical sidewalls; removing, through the second vertical opening, portions of the third dielectric material to form a third horizontal opening; and forming a metal in the third horizontal opening to form a horizontally oriented digit line, wherein the metal contacts the second source/drain material.
19 . The method of claim 18 , wherein the method includes forming, through the second vertical opening, a fourth horizontal opening by removing second portions of the first source/drain material, second portions of the channel material, and second portions of the second source/drain material.
20 . The method of claim 17 , wherein the method includes forming the second horizontal opening prior to forming the first horizontal opening.

Description

PRIORITY INFORMATION This application is a Continuation of U.S. Application Serial No. 17/961,177, filed October 6, 2022, which issues as U.S. Patent No. 12,256,978 on January 13, 2026, which is a Continuation of U.S. Application Serial No. 17/093,869, filed on November 10, 2020, which issued as U.S. Patent No. 11,495,600 on November 8, 2022, the contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates generally to memory devices, and more particularly, to a three-dimensional memory having a vertically oriented access device with a vertical channel. BACKGROUND Memory is often implemented in electronic systems, such as computers, cell phones, hand-held devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and may include random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM). Non-volatile memory may provide persistent data by retaining stored data when not powered and may include NAND flash memory, NOR flash memory, nitride read only memory (NROM), phase-change memory, e.g., phase-change random access memory, resistive memory, e.g., resistive random-access memory, cross-point memory, ferroelectric random-access memory (FeRAM), or the like. As design rules shrink, less semiconductor space is available to fabricate memory, including DRAM arrays. A respective memory cell for DRAM may include an access device, e.g., transistor, having a first and a second source/drain regions separated by a channel region. A gate may oppose the channel region and be separated therefrom by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the access device. A DRAM cell can include a storage node, such as a capacitor cell, coupled by the access device to a digit line. The access device can be enabled, e.g., to select the cell, by activating the access line to which its gate is coupled. The capacitor can store a charge corresponding to a data value of a respective cell, e.g., a logic “1” or “0”. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic illustration of a vertical three-dimensional (3D) memory in accordance a number of embodiments of the present disclosure. FIG. 2 is a perspective view illustrating a portion of a semiconductor devices in accordance with a number of embodiments of the present disclosure. FIG. 3A-3V illustrate portions of vertically stacked memory cells, at various stages of a fabrication process, in accordance with a number of embodiments of the present disclosure. FIG. 4 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure. DETAILED DESCRIPTION Embodiments of the present disclosure describe a three-dimensional memory having a vertically oriented access device having a vertical channel. The three-dimensional memory, which may be referred to as a semiconductor device, also includes a horizontally oriented storage node. The vertically oriented access device is vertically adjacent to the horizontally oriented storage node. Utilizing these access devices and storage nodes can help provide an increased width of the access device, as compared to other semiconductor device schemes. Also, utilizing these access devices and storage nodes can help provide a reduced footprint, as compared to other semiconductor device schemes. Providing 3D memory cells in accordance with embodiments described herein can help to provide reduced mobility constraints and/or a reduced operating voltage, as compared to other memory cell schemes. The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, reference numeral 111 may reference element “11” in FIG. 1, and a similar element may be referenced as 211 in FIG. 2. Multiple analogous elements within one figure may be referenced with a reference numeral followed by a hyphen and another numeral or a letter. For example, 103-1 may reference element 103-1 in FIG. 1and 103-2 may reference element 103-2, which may be analogous to element 103-1. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements 103-1 and 103-2 or other analogous elements may be generally referenced as 103. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided