US-20260129830-A1 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

US20260129830A1US 20260129830 A1US20260129830 A1US 20260129830A1US-20260129830-A1

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes a substrate and a semiconductor component located on the substrate; the semiconductor component includes a channel structure, a first electrode, a gate electrode, and a second electrode; the first electrode, the gate electrode, and the second electrode are spaced apart and sequentially stacked in a vertical direction. The channel structure comprises a channel layer and a gate insulating layer, the channel layer extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode. The gate insulating layer is located between the gate electrode and the channel layer. According to the solution of the present disclosure, the channel layer has better crystallization characteristics while it can have a variety of shape structures.

Inventors

Jinghao WANG

Assignees

SWAYSURE TECHNOLOGY CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250925
Priority Date: 20241106

Claims (20)

1 . A semiconductor device, comprising: a substrate and a semiconductor component located on the substrate; wherein the semiconductor component comprises a channel structure and a first electrode, a gate electrode and a second electrode, the first electrode, the gate electrode and the second electrode are spaced apart and stacked sequentially in a vertical direction, the channel structure comprises a channel layer and a gate insulating layer, the channel structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.
2 . The semiconductor device of claim 1 , further comprising a first insulating layer prepared in the same layer as the gate insulating layer and extending horizontally between the first electrode and the gate electrode.
3 . The semiconductor device of claim 2 , wherein: the first insulating layer is in contact with the first electrode, and the first insulating layer is in contact with the gate electrode
4 . The semiconductor device of claim 1 , wherein: a distance between an end of the channel layer connected to the second electrode and the gate electrode is smaller than a distance between an end of the gate insulating layer in contact with the second electrode and the gate electrode.
5 . The semiconductor device of claim 4 , wherein: the second electrode comprises a first portion in contact with the channel layer, and a second portion located on a side of the first portion away from the channel layer; the semiconductor device further comprises an insulating dielectric layer located between the second portion and the gate electrode, and an orthographic projection of the insulating dielectric layer on the substrate does not overlap with an orthographic projection of the channel structure on the substrate.
6 . The semiconductor device of claim 1 , wherein: the semiconductor device further comprises a first signal line formed integrally with the first electrode and extending in a first horizontal direction, and an orthographic projection of the first electrode on the substrate is located within an orthographic projection of the first signal line on the substrate.
7 . The semiconductor device of claim 6 , wherein: an orthographic projection boundary of the channel layer on the substrate exceeds the orthographic projection of the first signal line on the substrate; or an orthographic projection boundary of the channel layer on the substrate partially overlaps with an edge of the orthographic projection of the first signal line on the substrate and does not exceed the orthographic projection of the first signal line.
8 . The semiconductor device of claim 1 , wherein: an orthographic projection of the channel structure on the substrate comprises a ring, and an orthographic projection of the gate electrode on the substrate comprises a third portion located inside the ring and a fourth portion located outside the ring.
9 . The semiconductor device of claim 1 , wherein: an orthographic projection of the channel structure on the substrate comprises a plurality of fifth portions; the gate electrode comprises a sixth portion surrounding each of the fifth portions, and the sixth portion in the gate electrode is formed integrally; wherein: orthographic projections of the fifth portions on the substrate are strip-shaped and parallel to each other; or orthographic projections of the fifth portions on the substrate are rings, and the gate electrode further comprises seventh portions located inside the rings.
10 . The semiconductor device of claim 1 , wherein: the first electrode comprises a first contact material layer and a conductor layer, wherein the first contact material layer is disposed between the conductor layer and the channel layer; and the second electrode comprises a second contact material layer.
11 . A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate; sequentially preparing a first electrode, a channel layer, a gate insulating layer and a gate electrode on the substrate; and preparing a second electrode on the substrate; wherein the channel layer extends in a vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.
12 . The method of claim 11 , wherein preparing the channel layer comprises: preparing a semiconductor material layer on the first electrode; preparing a first patterned mask layer on the semiconductor material layer; and using the first patterned mask layer as a mask to etch the semiconductor material layer to form the channel layer.
13 . The method of claim 12 , wherein: the first patterned mask layer comprises at least one portion, and an orthographic projection of the portion on the substrate comprises a ring or a rectangle; and/or an orthographic projection of the first patterned mask layer on the substrate comprises a plurality of parallel strips.
14 . The method of claim 12 , wherein preparing the second electrode comprises: preparing a contact material layer on the semiconductor material layer before preparing the first patterned mask layer; and patterning the contact material layer to form an upper contact portion while etching the semiconductor material layer using the first patterned mask layer as a mask; wherein the second electrode comprises the upper contact portion.
15 . The method of claim 14 , the method further comprises: preparing a first signal line, the first signal line and the first electrode being prepared simultaneously, and an orthographic projection of the first electrode on the substrate being located within an orthographic projection of the first signal line on the substrate; preparing the gate insulating layer and the gate electrode comprises: preparing a gate insulating material layer that covers the channel layer, the upper contact portion, the first electrode and the first signal line; preparing a gate electrode material layer that covers the gate insulating material layer; patterning and etching the gate electrode material layer to form the gate electrode, wherein a surface of a side of the gate electrode away from the substrate is lower than the channel layer; preparing an insulating dielectric layer that covers the gate insulating material layer and the gate electrode; and removing a portion of the insulating dielectric layer and a portion of the gate insulating material layer to expose the upper contact portion, wherein the gate insulating material layer located on a side of the gate electrode close to the channel layer is formed as the gate insulating layer.
16 . The method of claim 15 , wherein the preparing the second electrode further comprises: preparing a connection portion at an end of the upper contact portion away from the channel layer after the upper contact portion is exposed, wherein the second electrode further comprises the connection portion.
17 . The method of claim 12 , wherein, in an orthographic projection on the substrate: the first patterned mask layer comprises a ring, and the gate electrode comprises a portion located inside the ring and a portion located outside the ring; or the first patterned mask layer comprises a plurality of portions, and the gate electrode surrounds each of the portions.
18 . The method of claim 12 , further comprising: preparing a first signal line, the first signal line and the first electrode being prepared simultaneously, and an orthographic projection of the first electrode on the substrate being located within an orthographic projection of the first signal line on the substrate; wherein an orthographic projection boundary of the first patterned mask layer on the substrate exceeds the orthographic projection of the first signal line on the substrate, or partially overlaps with an edge of the orthographic projection of the first signal line without exceeding the orthographic projection of the first signal line.
19 . The method of claim 12 , wherein the first electrode comprises a conductor layer and a lower contact portion located on a side of the conductor layer away from the substrate; after preparing the semiconductor material layer, the method further comprises the step of: performing heat treatment so as to reduce impedance between the semiconductor material layer and the lower contact portion.
20 . The method of claim 14 , wherein: after preparing the contact material layer on the semiconductor material layer, the method further comprises the step of: performing heat treatment so as to reduce impedance between the semiconductor material layer and the contact material layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims a priority to Chinese Patent Application No. 202411587561.6 filed on Nov. 6, 2024. The entire contents of the above-identified application are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the technical field of the semiconductor, specifically to a semiconductor device and a manufacturing method thereof. BACKGROUND Dynamic Random Access Memory (DRAM) is a semiconductor memory with the advantages such as large capacity and low cost, and has been widely used in various fields. The basic memory unit of conventional DRAM is 1T1C (1Transistor-1Capacitor) memory unit, which requires a transistor and a capacitor. With the development of three-dimensional memory process, the number of vertical channel transistor structures is increasing. In the transistor with the vertical channel structure, channel layer between the interconnect layers is controlled by the word line (WL) to act as a switch. However, the channel layer in the related art is often limited by a circular ring shape and is prepared after the WL, which results in the poor crystallization characteristics of the channel layer and thereby the declined electrical performance of the memory. SUMMARY A series of simplified concepts is introduced into the portion of Summary, which would be further illustrated in the portion of the detailed description. The Summary of the present disclosure does not mean attempting to define the key feature and essential technical feature of the claimed technical solution, let alone determining the protection scope thereof. In view of the existing problems, a first aspect of the present disclosure provides a semiconductor device, including: a substrate and a semiconductor component located on the substrate;the semiconductor component including a channel structure and a first electrode, a gate electrode and a second electrode, wherein the first electrode, the gate electrode and the second electrode are spaced apart and stacked sequentially in a vertical direction, the channel structure includes a channel layer and a gate insulating layer, the channel structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer. Exemplarily, the semiconductor device further includes a first insulating layer prepared in the same layer as the gate insulating layer and extending horizontally between the first electrode and the gate electrode. Exemplarily, the first insulating layer is in contact with the first electrode. Exemplarily, the first insulating layer is in contact with the gate electrode. Exemplarily, a distance between one end of the channel layer connected to the second electrode and the gate electrode is smaller than a distance between one end of the gate insulating layer in contacting with the second electrode and the gate electrode. Exemplarily, the second electrode includes a first portion in contact with the channel layer, and a second portion located on a side of the first portion away from the channel layer; the semiconductor device further includes an insulating dielectric layer located between the second portion and the gate electrode, and an orthographic projection of the insulating dielectric layer on the substrate does not overlap with an orthographic projection of the channel structure on the substrate. Exemplarily, the semiconductor device further includes a first signal line formed integrally with the first electrode and extending in a first horizontal direction, and an orthographic projection of the first electrode on the substrate is located within an orthographic projection of the first signal line on the substrate. Exemplarily, an orthographic projection boundary of the channel layer on the substrate exceeds the orthographic projection of the first signal line on the substrate; or an orthographic projection boundary of the channel layer on the substrate partially overlaps with an edge of the orthographic projection of the first signal line on the substrate and does not exceed the orthographic projection of the first signal line. Exemplarily, an orthographic projection of the channel structure on the substrate includes a ring, and an orthographic projection of the gate electrode on the substrate includes a third portion located inside the ring and a fourth portion located outside the ring. Exemplarily, an orthographic projection of the channel structure on the substrate includes a plurality of fifth portions; the gate electrode includes a sixth portion surrounding each of the fifth portions, and the sixth portion in the gate electrode is formed integrally. Exemplarily, orthographic projections of the fifth portions on the substrate are strip-shaped and parallel to each other; or An orthographic projection of a fifth portion on the substrate is a r