US-20260129832-A1 - SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL LAYER AND METHOD FOR FABRICATING THE SAME

US20260129832A1US 20260129832 A1US20260129832 A1US 20260129832A1US-20260129832-A1

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

Inventors

Tseng-Fu Lu

Assignees

NANYA TECHNOLOGY CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241211

Claims (12)

1 . A semiconductor device, comprising: a substrate; a channel layer positioned over the substrate and extending along a first direction perpendicular to a top surface of the substrate, wherein a width of a top surface of the channel layer is greater than a width of a bottom surface of the channel layer; and a word line comprising: a word-line dielectric layer conformally and laterally surrounding the channel layer; and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer and extending along a second direction parallel to the top surface of the substrate, wherein a width of a top surface of the word-line conductive layer is greater than a width of a bottom surface of the word-line conductive layer; wherein the word-line dielectric layer comprises a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
2 . The semiconductor device of claim 1 , further comprising a bit line positioned under the channel layer and electrically coupled to the channel layer.
3 . The semiconductor device of claim 2 , further comprising a bit-line contact positioned between the channel layer and the bit-line contact.
4 . The semiconductor device of claim 3 , wherein the bit line is positioned in the substrate and extending along a third direction perpendicular to the second direction.
5 . The semiconductor device of claim 3 , wherein the bit line is positioned on the substrate and extending along a third direction perpendicular to the second direction.
6 . The semiconductor device of claim 3 , further comprising a storage node structure positioned on the channel layer and electrically connected to the channel layer.
7 . The semiconductor device of claim 6 , wherein the storage node structure comprises: a first electrode layer positioned on the channel layer and electrically connected to the channel layer; a second electrode layer positioned on the first electrode layer; and a middle insulating layer positioned between the first electrode layer and the second electrode layer to electrically isolate the first electrode layer and the second electrode layer.
8 . The semiconductor device of claim 1 , further comprising a bit line positioned on the channel layer and electrically coupled to the channel layer.
9 . The semiconductor device of claim 8 , further comprising a bit-line contact positioned between the bit line and the channel layer.
10 . The semiconductor device of claim 9 , further comprising a storage node structure positioned under the channel layer and electrically connected to the channel layer.
11 . The semiconductor device of claim 1 , wherein the channel layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium.
12 . The semiconductor device of claim 1 , wherein the word-line conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of U.S. Non-Provisional application Ser. No. 18/938,457 filed Nov. 6, 2024, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with a vertical channel layer and a method for fabricating the semiconductor device with the vertical channel layer. DISCUSSION OF THE BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. SUMMARY One aspect of the present disclosure provides a semiconductor device including a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile. Another aspect of the present disclosure provides a semiconductor device including a substrate; a channel layer positioned over the substrate and extending along a first direction perpendicular to a top surface of the substrate, wherein a width of a top surface of the channel layer is greater than a width of a bottom surface of the channel layer; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer and extending along a second direction parallel to the top surface of the substrate, wherein a width of a top surface of the word-line conductive layer is greater than a width of a bottom surface of the word-line conductive layer. Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate; forming a lower dielectric layer over the substrate; forming a middle dielectric layer on the lower dielectric layer; forming a word-line trench penetrating the middle dielectric layer, exposing the lower dielectric layer, and including an inverted trapezoid cross-sectional profile; forming a word-line conductive layer filling the word-line trench; forming an upper dielectric layer on the middle dielectric layer; forming a channel opening penetrating the upper dielectric layer, the word-line conductive layer, and the lower dielectric layer to expose the substrate; and conformally forming a word-line dielectric layer on a sidewall of the channel opening; and forming a channel layer filling the channel opening. The word-line conductive layer and the word-line dielectric layer together configure a word line. Due to the design of the semiconductor device of the present disclosure, the process window for forming the channel layer may be increased by employing the word-line conductive layer and the channel layer with the inverted trapezoid cross-sectional profile. As a result, the defect for fabricating the semiconductor device may be decreased and the yield for fabricating the semiconductor device may be improved. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in