US-20260129834-A1 - SEMICONDUCTOR DEVICE

US20260129834A1US 20260129834 A1US20260129834 A1US 20260129834A1US-20260129834-A1

Abstract

A semiconductor device includes a substrate, a bit line positioned on the substrate and extending in a first direction, word lines extending in a second direction, a first active pattern and a second active pattern positioned between the word lines and spaced apart in the first direction, a cell capacitor positioned on the first active pattern and the second active pattern, and shield gates positioned at a level between the word lines and the cell capacitor. Each of the first active pattern and the second active pattern includes a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a channel region positioned between the first dopant region and the second dopant region. The shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.

Inventors

Moonyoung JEONG
Sangho Lee
Jae Hyun Choi

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250523
Priority Date: 20241106

Claims (20)

1 . A semiconductor device comprising: a substrate; a bit line that is positioned on the substrate and extends in a first direction; a plurality of word lines that extend in a second direction intersecting the first direction; a first active pattern and a second active pattern that are positioned between the plurality of word lines and spaced apart in the first direction; a cell capacitor that is positioned on the first active pattern and the second active pattern; and a plurality of shield gates that are positioned at a level between the plurality of word lines and the cell capacitor, wherein each of the first active pattern and the second active pattern includes the following: a first dopant region that is connected to the bit line; a second dopant region that is connected to the cell capacitor; and a channel region that is positioned between the first dopant region and the second dopant region, and the plurality of shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.
2 . The semiconductor device of claim 1 , wherein: the plurality of shield gates overlap the plurality of word lines in a vertical direction intersecting the first direction and the second direction.
3 . The semiconductor device of claim 1 , further comprising: a back gate electrode that is positioned between the first active pattern and the second active pattern and extends in the second direction.
4 . The semiconductor device of claim 3 , wherein: the plurality of shield gates include the following: a first shield gate that overlaps the back gate electrode in a vertical direction intersecting the first direction and the second direction; and a second shield gate that overlaps the plurality of word lines in the vertical direction.
5 . The semiconductor device of claim 4 , wherein: the back gate electrode and the first shield gate are configured to be applied with different voltages, and the plurality of word lines and the second shield gate are configured to be applied with different voltages.
6 . The semiconductor device of claim 4 , wherein: the back gate electrode and the first shield gate are configured to be applied with a same voltage, the plurality of word lines and the second shield gate are configured to be applied with a same voltage, the first shield gate has a work function different from that of the back gate electrode, and the second shield gate has a work function different from that of the plurality of word lines.
7 . The semiconductor device of claim 1 , further comprising: an insulating isolation pattern that is positioned between the first active pattern and the second active pattern, wherein the plurality of shield gates include the following: a first shield gate that overlaps the isolation insulating pattern in a vertical direction intersecting the first direction and the second direction; and a second shield gate that overlaps the plurality of word lines in the vertical direction.
8 . A semiconductor device comprising: a substrate that includes a cell array region and a peripheral circuit region; a bit line that is positioned on the cell array region and extends in a first direction; a plurality of word lines that extend in a second direction intersecting the first direction; a first active pattern and a second active pattern that are positioned on the plurality of word lines and spaced apart in the first direction; a back gate electrode that is positioned between the first active pattern and the second active pattern and extends in the second direction; a cell capacitor that is positioned on the first active pattern and the second active pattern; and a plurality of shield gates that overlap at least one of the plurality of word lines and the back gate electrode in a vertical direction intersecting the first direction and the second direction, wherein each of the first active pattern and the second active pattern includes the following: a first dopant region that is connected to the bit line; a second dopant region that is connected to the cell capacitor; and a channel region that is positioned between the first dopant region and the second dopant region, and the plurality of shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.
9 . The semiconductor device of claim 8 , wherein: the plurality of shield gates includes the following: a first shield gate that overlaps the back gate electrode in the vertical direction; and a second shield gate that overlaps the plurality of word lines in the vertical direction.
10 . The semiconductor device of claim 9 , wherein: a width of the first shield gate and a width of the second shield gate are different.
11 . The semiconductor device of claim 9 , wherein: a width of the second shield gate is smaller than a width of each of the plurality of word lines.
12 . The semiconductor device of claim 11 , wherein: a width of the first shield gate is smaller than a width of the back gate electrode.
13 . The semiconductor device of claim 9 , wherein: the plurality of word lines includes a first word line and a second word line adjacent to each other, and the second shield gate overlaps the first word line and the second word line in the vertical direction.
14 . The semiconductor device of claim 9 , wherein: an upper surface of the first shield gate and an upper surface of the second shield gate are positioned at different levels.
15 . The semiconductor device of claim 9 , wherein: a thickness of the first shield gate and a thickness of the second shield gate are different.
16 . The semiconductor device of claim 9 , wherein: in the peripheral circuit region, ends of the first shield gate and the back gate electrode are aligned at substantially the same boundary, and the semiconductor device further includes the following: a contact wiring line that is positioned in the peripheral circuit region; a first contact via that is connected to the contact wiring line and the back gate electrode; and a second contact via that is connected to the contact wiring line and the first shield gate and passes through the back gate electrode.
17 . The semiconductor device of claim 9 , wherein: in the peripheral circuit region, the second shield gate and the plurality of word lines extend with different lengths so as to have a stepped structure, and the semiconductor device further includes the following: a word line contact that is positioned in the peripheral circuit region and connected to the plurality of word lines; and a second shield gate contact that is positioned in the peripheral circuit region and connected to the second shield gate on an outer side than ends of the plurality of word lines.
18 . A semiconductor device comprising: a substrate that includes a cell array region and a peripheral circuit region; a peripheral circuit structure that includes a peripheral circuit which is positioned on the substrate, and a peripheral circuit wiring line which is connected to the peripheral circuit; and a cell structure that overlaps the peripheral circuit structure in a vertical direction, wherein the cell structure includes the following: a bit line that is positioned on the substrate and extends in a first direction intersecting the vertical direction; a plurality of word lines that extend in a second direction intersecting the first direction and the vertical direction; a plurality of active patterns that are positioned between the plurality of word lines and spaced apart in the first direction; a back gate electrode that is positioned between the plurality of active patterns and extends in the second direction; a cell capacitor that is positioned on the plurality of active patterns; a first shield gate that overlaps the back gate electrode in the vertical direction; and a second shield gate that overlaps the plurality of word lines in the vertical direction, and each of the plurality of active patterns includes the following: a first dopant region that is connected to the bit line; a second dopant region that is connected to the cell capacitor; and a channel region that is positioned between the first dopant region and the second dopant region, and each of the first shield gate and the second shield gate overlaps the second dopant region in the first direction.
19 . The semiconductor device of claim 18 , wherein: the peripheral circuit structure further includes a first bonding pad, and a first bonding insulating layer that surrounds the first bonding pad, the cell structure further includes a second bonding pad, and a second bonding insulating layer that surrounds the second bonding pad, and the first bonding pad is in contact with the second bonding pad, and the first bonding insulating layer is in contact with the second bonding insulating layer.
20 . The semiconductor device of claim 18 , wherein: the cell structure further includes a memory cell and a cell connection wiring line which is connected to the memory cell, and the semiconductor device further includes a through-hole via which connects the peripheral circuit wiring line and the cell connection wiring line.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0156558 filed in the Korean Intellectual Property Office on Nov. 6, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE DISCLOSURE 1. Field The present disclosure relates to a semiconductor device. 2. Description of the Related Art There is a need for technologies to increase the degrees of integration of semiconductor devices. In the case of two-dimensional semiconductor devices, the degrees of integration are mainly determined by the areas occupied by unit memory cells, and the degrees of integration in this aspect may depend on the levels of micropatterning techniques. By the way, the micropatterning techniques require expensive equipment. Therefore, although the degrees of integration of two-dimensional semiconductor devices are increasing, it is still limited. Accordingly, three-dimensional memory devices having memory cells arranged in three dimensions are being proposed. As components which are included in semiconductor memory devices become more integrated and miniaturized, it is important to minimize the influence between components included in semiconductor devices to improve the operating performance of the semiconductor devices. SUMMARY The present disclosure attempts to provide a semiconductor device with improved reliability and productivity. A semiconductor device according to an embodiment includes a substrate, a bit line that is positioned on the substrate and extends in a first direction, a plurality of word lines that extend in a second direction intersecting the first direction, a first active pattern and a second active pattern that are positioned between the plurality of word lines and spaced apart in the first direction, a cell capacitor that is positioned on the first active pattern and the second active pattern, and a plurality of shield gates that are positioned at a level between the plurality of word lines and the cell capacitor, and each of the first active pattern and the second active pattern includes a first dopant region that is connected to the bit line, a second dopant region that is connected to the cell capacitor, and a channel region that is positioned between the first dopant region and the second dopant region, and the plurality of shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction. A semiconductor device according to an embodiment includes a substrate that includes a cell array region and a peripheral circuit region, a bit line that is positioned on the cell array region and extends in a first direction, a plurality of word lines that extend in a second direction intersecting the first direction, a first active pattern and a second active pattern that are positioned on the plurality of word lines and spaced apart in the first direction, a back gate electrode that is positioned between the first active pattern and the second active pattern and extends in the second direction, a cell capacitor that is positioned on the first active pattern and the second active pattern, and a plurality of shield gates that overlap at least one of the plurality of word lines and the back gate electrode in a vertical direction intersecting the first direction and the second direction, and each of the first active pattern and the second active pattern includes a first dopant region that is connected to the bit line, a second dopant region that is connected to the cell capacitor, and a channel region that is positioned between the first dopant region and the second dopant region, and the plurality of shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction. A semiconductor device according to an embodiment includes a substrate that includes a cell array region and a peripheral circuit region, a peripheral circuit structure that includes a peripheral circuit which is positioned on the substrate, and a peripheral circuit wiring line which is connected to the peripheral circuit, and a cell structure that overlaps the peripheral circuit structure in a vertical direction, and the cell structure includes a bit line that is positioned on the substrate and extends in a first direction intersecting the vertical direction, a plurality of word lines that extend in a second direction intersecting the first direction and the vertical direction, a plurality of active patterns that are positioned between the plurality of word lines and spaced apart in the first direction, a back gate electrode that is positioned between the plurality of active patterns and extends in the second direction, a cell capacitor that is positioned on the plurality of active patterns, a first shield gate that overlaps the back gate electrode in the vertical direction, and a second shiel