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US-20260129835-A1 - SEMICONDUCTOR DEDVICE AND METHOD FOR FABRICATING THE SAME

US20260129835A1US 20260129835 A1US20260129835 A1US 20260129835A1US-20260129835-A1

Abstract

Disclosed is a semiconductor device which includes a first gate that extends in a first direction, an island gate adjacent to one end of the first gate in the first direction, a second gate that is spaced apart from the first gate in a second direction perpendicular to the first direction and that extends in the first direction, and a contact plug in contact with the island gate and the second gate.

Inventors

  • Yeon Gyu LEE
  • Min Chul SUNG
  • Seung Wook Ryu

Assignees

  • SK Hynix Inc.

Dates

Publication Date
20260507
Application Date
20251020
Priority Date
20241106

Claims (20)

  1. 1 . A semiconductor device comprising: a first gate configured to extend in a first direction; an island gate adjacent to one end of the first gate in the first direction; a second gate spaced apart from the first gate in a second direction perpendicular to the first direction and configured to extend in the first direction; and a contact plug in contact with the island gate and the second gate.
  2. 2 . The semiconductor device of claim 1 , wherein the island gate has a quadrangular shape.
  3. 3 . The semiconductor device of claim 2 , wherein the second gate surrounds at least three sides of the island gate.
  4. 4 . The semiconductor device of claim 1 , wherein the second gate includes a bridge portion disposed between the island gate and the first gate.
  5. 5 . The semiconductor device of claim 1 , wherein the second gate contacts the island gate.
  6. 6 . The semiconductor device of claim 1 , further comprising: a bit line spaced apart from the first gate in a third direction perpendicular to the first direction and the second direction and configured to extend in the second direction.
  7. 7 . The semiconductor device of claim 6 , further comprising: an active region in contact with the bit line, wherein the active region includes a horizontal portion in contact with the bit line and configured to extend in the second direction and a vertical portion configured to extend in the third direction.
  8. 8 . The semiconductor device of claim 7 , wherein the vertical portion is disposed between the first gate and the second gate.
  9. 9 . The semiconductor device of claim 8 , wherein the first gate is disposed between the vertical portions included in the adjacent active regions, respectively.
  10. 10 . The semiconductor device of claim 8 , wherein the active region includes an oxide semiconductor.
  11. 11 . The semiconductor device of claim 1 , further comprising: a separation region configured to separate adjacent second gates from each other.
  12. 12 . The semiconductor device of claim 11 , wherein the separation region is disposed between the first gate and the island gate.
  13. 13 . The semiconductor device of claim 11 , wherein the separation region contacts one end of the second gate in the first direction.
  14. 14 . The semiconductor device of claim 1 , wherein a voltage provided to the first gate is different from a voltage provided to the second gate.
  15. 15 . The semiconductor device of claim 14 , wherein the voltage provided to the first gate is a ground voltage.
  16. 16 . The semiconductor device of claim 1 , further comprising: another island gate adjacent to an opposite end of the first gate in the first direction; and another contact plug electrically connected to the another island gate.
  17. 17 . The semiconductor device of claim 16 , wherein the contact plug and the another contact plug are disposed in a diagonal direction with respect to the center of the first gate.
  18. 18 . A semiconductor device comprising: a first gate configured to extend in a first direction; a bit line configured to extend in a second direction perpendicular to the first direction; a second gate spaced apart from the first gate in the second direction; an active region including a horizontal portion in contact with the bit line and a vertical portion configured to extend in a third direction perpendicular to the first direction and the second direction; an island gate adjacent to one end of the first gate in the first direction; and a contact plug configured to overlap with the island gate and the second gate, wherein the vertical portion is disposed between the first gate and the second gate.
  19. 19 . The semiconductor device of claim 18 , further comprising: a separation region configured to separate adjacent second gates from each other.
  20. 20 . A semiconductor device comprising: a first gate and a second gate extending in a first direction and spaced apart from each other in a second direction that is perpendicular to the first direction; and an island gate adjacent to a first end of the first gate; wherein the second gate surrounds three sides of the island gate, and wherein the second gate includes a bridge portion disposed between the island gate and the first gate.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of priority to Korean Patent Application No. 10-2024-0156248, filed on Nov. 6, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The embodiments of the present disclosure relate generally to a semiconductor device, and more particularly, relates to a semiconductor device including a memory cell. BACKGROUND As compactness of semiconductor devices and an improvement in the degree of integration thereof are emerging as a major issue, memory cells included in the semiconductor devices may be formed to have a three-dimensional pattern, and the operating characteristics of the memory cells may be improved. As semiconductor devices become more compact and highly integrated, memory cells within them are increasingly designed with three-dimensional structures. This 3D configuration enhances the operating performance of memory cells, helping overcome limitations of traditional 2D layouts and supporting the advancement of modern chip technology. Since these 3D structures are relatively new, ongoing research is focused on improving their structural integrity, reliability, and overall performance characteristics. SUMMARY The embodiments of the present disclosure have been made to solve issues occurring in the prior art while advantages achieved by the prior art are maintained intact. According to embodiments of the present disclosure, a three-dimensional semiconductor device is provided (hereinafter simply referred to as semiconductor device) which exhibits, among other improvements, improved integration. The semiconductor device according to an embodiment may include an island gate to improve contact stability between a gate and a contact plug included in the semiconductor device. In addition, the semiconductor device of the present disclosure may include an island gate connected to the contact plug for securing a margin for the formation of the contact plug and for reducing the difficulty level of the process. It is noted that the technical problems solved by the embodiments of the present disclosure are not limited to the aforementioned problems, and other technical problems not mentioned herein will be clearly understood from the following description by those having ordinary skill in the art to which the present disclosure pertains. According to an embodiment of the present disclosure, a semiconductor device includes a first gate that extends in a first direction, an island gate adjacent to one end of the first gate in the first direction, a second gate that is spaced apart from the first gate in a second direction perpendicular to the first direction and that extends in the first direction, and a contact plug in contact with the island gate and the second gate. According to an embodiment, the island gate may have a quadrangular shape, and the second gate may surround at least three sides of the island gate. According to an embodiment, the second gate may include a bridge portion disposed between the island gate and the first gate. According to an embodiment, the second gate may contact the island gate. According to an embodiment, the semiconductor device may further include a bit line that is spaced apart from the first gate in a third direction perpendicular to the first direction and the second direction and that extends in the second direction. According to an embodiment, the semiconductor device may further include an active region in contact with the bit line, and the active region may include a horizontal portion that is in contact with the bit line and extends in the second direction and a vertical portion that extends in the third direction. According to an embodiment, the vertical portion may be disposed between the first gate and the second gate. According to an embodiment, the first gate may be disposed between the vertical portions included in the adjacent active regions, respectively. According to an embodiment, the active region may include an oxide semiconductor. According to an embodiment, the semiconductor device may further include a separation region that separates adjacent second gates from each other. According to an embodiment, the separation region may be disposed between the first gate and the island gate. According to an embodiment, the separation region may contact one end of the second gate in the first direction. According to an embodiment, a voltage provided to the first gate may be different from a voltage provided to the second gate. According to an embodiment, the voltage provided to the first gate may be a ground voltage. According to an embodiment, the semiconductor device may further include another island gate adjacent to an opposite end of the first gate in the first direction and another contact plug electrically connected to the another island gate. According to an embodiment, the contact plug and the other contact plug may be disposed in a diagonal direction with