US-20260129836-A1 - SEMICONDUCTOR DEVICE

Abstract

A method for manufacturing a semiconductor device includes forming device isolation layers on a substrate, forming bitline structures on the substrate, forming a first preliminary spacer on the bitline structures, forming a sacrificial spacer on the first preliminary spacer, forming a second preliminary spacer on the sacrificial spacer and the substrate by performing a nitridation process, forming a third preliminary spacer on the second preliminary spacer, forming sacrificial patterns between the bitline structures and forming contact openings by etching the sacrificial patterns, forming storage node contacts in the contact openings, forming landing pads on the storage node contacts and forming recess regions between the landing pads by etching the bitline structures, the first to third preliminary spacers, and the sacrificial spacer, forming spacer structures including an air spacer by removing the exposed sacrificial spacer, and forming capacitor structures on the landing pads.

Inventors

• Jaewon NA
• Sungsam Lee
• TaiUk Rim
• Byungha KANG
• Kanghyun Kim

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251223

Priority Date

20220110

Claims (20)

1. 1 . A method for manufacturing a semiconductor device, comprising: forming device isolation layers on a substrate, the device isolation layers defining an active region; forming bitline structures on the substrate, each of the bitline structures including a bitline and a bitline capping pattern sequentially stacked; forming a first preliminary spacer on the bitline structures; forming a sacrificial spacer on the first preliminary spacer; forming a second preliminary spacer on the sacrificial spacer and the substrate by performing a nitridation process; forming a third preliminary spacer on the second preliminary spacer; forming sacrificial patterns between the bitline structures and forming contact openings by etching the sacrificial patterns; forming storage node contacts in the contact openings, the storage node contacts being between the bitline structures; forming landing pads on the storage node contacts and forming recess regions between the landing pads by etching the bitline structures, the first to third preliminary spacers, and the sacrificial spacer using the landing pads as an etching mask; forming spacer structures including an air spacer by removing an exposed portion of the sacrificial spacer at the recess regions; and forming capacitor structures on the landing pads, wherein the spacer structures include a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on a sidewall of each of the bitline structures, wherein the second spacer is the air spacer, wherein the third spacer has a thickness that is less than a thickness of the first spacer, wherein the second spacer includes a first portion is spaced apart from the fourth spacer by the third spacer, and wherein the first portion of the second spacer is at a level that is higher than a level of an uppermost surface of the bitline.
2. 2 . The method as claimed in claim 1 , wherein the thickness of the third spacer is less than a thickness of the fourth spacer.
3. 3 . The method as claimed in claim 2 , wherein the thickness of the third spacer is within a range of 5 angstroms to 10 angstroms.
4. 4 . The method as claimed in claim 1 , wherein the nitridation process is a plasma nitridation process.
5. 5 . The method as claimed in claim 4 , wherein the sacrificial spacer includes a silicon oxide.
6. 6 . The method as claimed in claim 1 , wherein the third spacer includes a silicon oxynitride, and wherein the first spacer and the fourth spacer include a silicon nitride.
7. 7 . The method as claimed in claim 6 , wherein an oxygen content of the third spacer is higher than an oxygen content of the fourth spacer.
8. 8 . The method as claimed in claim 6 , wherein a density of the third spacer is lower than a density of the fourth spacer.
9. 9 . The method as claimed in claim 1 , wherein a lowermost surface of the third spacer is on a level that is lower than a level of a lowermost surface of the second spacer.
10. 10 . The method as claimed in claim 1 , further comprising: forming barrier patterns on the substrate before the forming the bitline structures, wherein the bitline structures are disposed on the barrier patterns, and the second preliminary spacer covers at least a portion of a side surface of the barrier patterns.
11. 11 . The method as claimed in claim 10 , wherein the barrier patterns include a first barrier pattern and a second barrier pattern, sequentially stacked, wherein the first barrier pattern includes a silicon oxide, the second barrier pattern includes a silicon nitride, and wherein the second preliminary spacer is in contact with at least one of the first barrier pattern and the second barrier pattern.
12. 12 . The method as claimed in claim 10 , wherein the first preliminary spacer includes: a vertical extension portion extending along the side surface of the bitline and the side surface of the bitline capping pattern, and a horizontal extension portion covering a portion of an upper surface of the barrier patterns, wherein the second spacer is on the horizontal extension portion, and wherein the third spacer is in contact with the horizontal extension portion.
13. 13 . The method as claimed in claim 1 , wherein the bitline structures further include a bitline contact pattern electrically connected to the active region, wherein the spacer structures further includes a bitline contact spacer surrounding a sidewall of the bitline contact pattern, and wherein the fourth spacer is spaced apart from the bitline contact spacer.
14. 14 . A method for manufacturing a semiconductor device, comprising: forming device isolation layers on a substrate, the device isolation layers defining an active region; forming barrier patterns the device isolation layers and the active region; forming bitline structures on the substrate and the barrier patterns, each of the bitline structures including a bitline and a bitline capping pattern sequentially stacked; forming a first preliminary spacer on the bitline structures; forting a sacrificial spacer on the first preliminary spacer; forming a second preliminary spacer on the sacrificial spacer and the barrier patterns by performing a nitridation process; forming a third preliminary spacer on the second preliminary spacer; forming sacrificial patterns between the bitline structures and forming contact openings by etching the sacrificial patterns; forming storage node contacts in the contact openings, the storage node contacts being between the bitline structures; forming landing pads on the storage node contacts and forming recess regions between the landing pads by etching the bitline structures, the first to third preliminary spacers, and the sacrificial spacer using the landing pads as an etching mask; forming spacer structures including an air spacer by removing an exposed portion of the sacrificial spacer at the recess regions; and forming capacitor structures on the landing pads, wherein the spacer structures include a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on a sidewall of each of the bitline structures, wherein the second spacer is the air spacer, wherein the third spacer and the fourth spacer include different materials from one another, and wherein a lowermost surface of the third spacer is on a level that is lower than a level of a lowermost surface of the second spacer.
15. 15 . The method as claimed in claim 14 , wherein the third spacer further includes a portion extending toward the substrate from a side surface of the second spacer.
16. 16 . The method as claimed in claim 14 , wherein the third spacer has a thickness that is less than a thickness of the first spacer and less than a thickness of the fourth spacer.
17. 17 . The method as claimed in claim 14 , wherein the first spacer and the fourth spacer each include a silicon nitride, and wherein the third spacer includes a silicon oxynitride.
18. 18 . The method as claimed in claim 14 , wherein the barrier patterns include a first barrier pattern and a second barrier pattern, sequentially stacked, wherein the first barrier pattern includes a silicon oxide, the second barrier pattern includes a silicon nitride, and wherein the second preliminary spacer is in contact with at least one of the first barrier pattern and the second barrier pattern.
19. 19 . A method for manufacturing a semiconductor device, comprising: forming device isolation layers on a substrate, the device isolation layers defining an active region; forming bitline structures on the substrate, each of the bitline structures including a bitline and a bitline capping pattern sequentially stacked; forming a first preliminary spacer on the bitline structures; forming a sacrificial spacer on the first preliminary spacer; forming a second preliminary spacer on the sacrificial spacer and the substrate; forming a third preliminary spacer on the second preliminary spacer; forming sacrificial patterns between the bitline structures and forming contact openings by etching the sacrificial patterns; forming storage node contacts in the contact openings, the storage node contacts being between the bitline structures; forming landing pads on the storage node contacts and forming recess regions between the landing pads by etching the bitline structures, the first to third preliminary spacers, and the sacrificial spacer using the landing pads as an etching mask; forming spacer structures including an air spacer by removing an exposed portion of the sacrificial spacer at the recess regions; and forming capacitor structures on the landing pads, wherein the spacer structures include a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on a sidewall of each of the bitline structures, wherein the second spacer is the air spacer, wherein the third spacer includes a silicon oxynitride, and wherein the third spacer has a maximum thickness in a horizontal direction that is less than a maximum thickness of the first spacer in the horizontal direction, less than a maximum thickness of the second spacer in the horizontal direction, and less than a maximum thickness of the fourth spacer in the horizontal direction.
20. 20 . The method as claimed in claim 19 , wherein the maximum thickness of the third spacer is within a range of 5 angstroms to 10 angstroms.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 17/959,634, filed on Oct. 4, 2022, and claims benefit of priority to Korean Patent Application No. 10-2022-0003187 filed on Jan. 10, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Embodiments relate to a semiconductor device. 2. Description of the Related Art With the development of the electronics industry and increasing demands of users, electronic devices have become more compact and multifunctional. SUMMARY According to an aspect of the present inventive concept, a method for manufacturing a semiconductor device, comprises forming device isolation layers on a substrate, the device isolation layers defining an active region; forming bitline structures on the substrate, each of the bitline structures including a bitline and a bitline capping pattern sequentially stacked; forming a first preliminary spacer on the bitline structures; forming a sacrificial spacer on the first preliminary spacer; forming a second preliminary spacer on the sacrificial spacer and the substrate by performing a nitridation process; forming a third preliminary spacer on the second preliminary spacer; forming sacrificial patterns between the bitline structures and forming contact openings by etching the sacrificial patterns; forming storage node contacts in the contact openings, the storage node contacts being between the bitline structures; forming landing pads on the storage node contacts and forming recess regions between the landing pads by etching the bitline structures, the first to third preliminary spacers, and the sacrificial spacer using the landing pads as etching mask; forming spacer structures including an air spacer by removing the exposed sacrificial spacer at the recess regions; and forming capacitor structures on the landing pads, wherein the spacer structures include a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on a sidewall of the bitline structure, the second spacer is the air spacer, the third spacer has a thickness that is less than a thickness of the first spacer, the second spacer includes a first portion is spaced apart from the fourth spacer by the third spacer, and the first portion of the second spacer is at a level that is higher than a level of an uppermost surface of the bitline. According to an aspect of the present inventive concept, a method for manufacturing a semiconductor device, comprises forming device isolation layers on a substrate, the device isolation layers defining an active region; forming barrier patterns the device isolation layers and the active region; forming bitline structures on the substrate and the barrier patterns, each of the bitline structures including a bitline and a bitline capping pattern sequentially stacked; forming a first preliminary spacer on the bitline structures; forting a sacrificial spacer on the first preliminary spacer; forming a second preliminary spacer on the sacrificial spacer and the barrier patterns by performing a nitridation process; forming a third preliminary spacer on the second preliminary spacer; forming sacrificial patterns between the bitline structures and forming contact openings by etching the sacrificial patterns; forming storage node contacts in the contact openings, the storage node contacts being between the bitline structures; forming landing pads on the storage node contacts and forming recess regions between the landing pads by etching the bitline structures, the first to third preliminary spacers, and the sacrificial spacer using the landing pads as etching mask; forming spacer structures including an air spacer by removing the exposed sacrificial spacer at the recess regions; and forming capacitor structures on the landing pads, wherein the spacer structures include a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on a sidewall of the bitline structure, the second spacer is the air spacer, the third spacer and the fourth spacer include different materials from one another, and a lowermost surface of the third spacer is on a level that is lower than a level of a lowermost surface of the second spacer. According to an aspect of the present inventive concept, a method for manufacturing a semiconductor device, comprises forming device isolation layers on a substrate, the device isolation layers defining an active region; forming bitline structures on the substrate, each of the bitline structures including a bitline and a bitline capping pattern sequentially stacked; forming a first preliminary spacer on the bitline structures; forming a sacrificial spacer on the first preliminary spacer; forming a second preliminary spacer on the sacrificial spacer and the substrate; forming a third preliminary spacer on the second preliminary spacer; forming s