US-20260129837-A1 - DRAIN SHARING FOR MEMORY CELL THIN FILM ACCESS TRANSISTORS AND METHODS FOR FORMING THE SAME

Abstract

A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.

Inventors

• Katherine H. Chiang
• Ken-Ichi Goto
• Chia Yu Ling
• Neil Quinn Murray
• Chung-Te Lin

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date

20260507

Application Date

20251230

Claims (20)

1. 1 . A method of forming a semiconductor structure, the method comprising: forming a first bottom word line and a second bottom word line extending along a first horizontal direction; forming a continuous bottom gate dielectric layer overlying the first bottom word line and the second bottom word line; forming a continuous metal oxide layer overlying the continuous bottom gate dielectric layer; forming a patterned masking layer overlying the continuous metal oxide layer, the patterned masking layer including a first line-shaped segment and a second line-shaped segment extending along the first horizontal direction and laterally spaced from each other along a second horizontal direction, the first line-shaped segment and the second line-shaped segment having a width less than a width of the first bottom word line and the second bottom word line; etching exposed portions of the continuous metal oxide layer and the continuous bottom gate dielectric layer using the patterned masking layer as an etch mask to form a metal oxide plate overlying the first bottom word line and the second bottom word line and the first gate dielectric and the second gate dielectric underlying the semiconducting metal oxide plate; forming a dielectric layer overlying the metal oxide plate; forming a first top gate trench, a second top gate trench, a first source cavity, a drain cavity, and a second source cavity extending through the dielectric layer; and forming a first gate electrode in the first top gate trench, a second gate electrode in the second top gate trench, a first source electrode in the first source cavity, a drain electrode in the drain cavity, and a second source electrode in the second source cavity.
2. 2 . The method of claim 1 , wherein: a top surface of the first gate dielectric and a top surface of second gate dielectric are physically exposed upon formation the first top gate trench and the second top gate trench; the first gate electrode is formed directly on the top surface of the first gate dielectric; and the second gate electrode is formed directly on the top surface of the second gate dielectric.
3. 3 . The method of claim 1 , wherein: top surface segments of the metal oxide plate are physically exposed upon formation of first source cavity, the drain cavity, and the second source cavity; and the first source electrode, the drain electrode, and the second source electrode are each formed with a barrier liner contacting the metal oxide plate, a fill conductive material overlying the barrier liner, a top surface coplanar with the dielectric layer after planarization, and straight sidewalls contacting the dielectric layer.
4. 4 . The method of claim 1 , further comprising: forming a first capacitor structure electrically connected to the first source electrode; and forming a second capacitor structure electrically connected to the second source electrode.
5. 5 . The method of claim 1 , wherein the first gate electrode and the second gate electrode are top word lines overlying respective channel regions in the metal oxide plate.
6. 6 . The method of claim 5 , wherein the first source cavity, the drain cavity, and the second source cavity have substantially vertical sidewalls.
7. 7 . The method of claim 6 , wherein forming the first source electrode, the drain electrode, and the second source electrode comprises forming, within the respective cavity, a liner conductive layer and a fill conductive layer.
8. 8 . A method of forming a semiconductor structure, the method comprising: forming a metal oxide plate extending along a first horizontal direction and having a first end region, a second end region, and a central region; forming a dielectric layer overlying the metal oxide plate; forming a first top gate trench, a second top gate trench, a first source cavity, a drain cavity, and a second source cavity extending through the dielectric layer; forming a first gate electrode in the first top gate trench, a second gate electrode in the second top gate trench, a first source electrode in the first source cavity, a drain electrode in the drain cavity, and a second source electrode in the second source cavity; forming a first capacitor structure electrically connected to the first source electrode; and forming a second capacitor structure electrically connected to the second source electrode.
9. 9 . The method of claim 8 , wherein: a top surface of the first gate dielectric and a top surface of second gate dielectric are exposed upon formation the first top gate trench and the second top gate trench; the first gate electrode is formed on the top surface of the first gate dielectric; and the second gate electrode is formed on the top surface of the second gate dielectric.
10. 10 . The method of claim 8 , wherein: top surface segments of the metal oxide plate are physically exposed upon formation of first source cavity, the drain cavity, and the second source cavity; and the first source electrode, the drain electrode, and the second source electrode have a top surface coplanar with the dielectric layer after planarization and straight sidewalls contacting the dielectric layer.
11. 11 . The method of claim 8 , wherein the first capacitor structure and the second capacitor structure are formed before forming the metal oxide plate.
12. 12 . The method of claim 8 , wherein the first top gate trench, the second top gate trench, the first source cavity, the drain cavity, and the second source cavity are arranged sequentially along the first horizontal direction.
13. 13 . The method of claim 8 , further comprising forming bit lines electrically connected to the drain electrode and extending parallel to the first horizontal direction.
14. 14 . The method of claim 8 , wherein the first capacitor structure and the second capacitor structure are arranged in a two-dimensional array with corresponding source electrodes.
15. 15 . A method of forming a semiconductor structure, the method comprising: forming a metal oxide plate extending along a first horizontal direction; forming gate structures adjacent the metal oxide plate to define a first channel region and a second channel region between first and second source regions and a shared drain region; forming a dielectric layer overlying the metal oxide plate; forming a first top gate trench, a second top gate trench, a first source cavity, a drain cavity, and a second source cavity extending through the dielectric layer; forming a first gate electrode in the first top gate trench, a second gate electrode in the second top gate trench, a first source electrode in the first source cavity, a drain electrode in the drain cavity, and a second source electrode in the second source cavity; forming a first capacitor structure electrically connected to the first source electrode; and forming a second capacitor structure electrically connected to the second source electrode.
16. 16 . The method of claim 15 , wherein: a top surface of the first gate dielectric and a top surface of second gate dielectric are exposed upon formation the first top gate trench and the second top gate trench; the first gate electrode is formed on the top surface of the first gate dielectric; and the second gate electrode is formed on the top surface of the second gate dielectric.
17. 17 . The method of claim 15 , wherein: top surface segments of the metal oxide plate are physically exposed upon formation of first source cavity, the drain cavity, and the second source cavity; and the first source electrode, the drain electrode, and the second source electrode are each formed with a barrier liner, a fill conductive material, a top surface coplanar with the dielectric layer after planarization, and straight sidewalls contacting the dielectric layer.
18. 18 . The method of claim 15 , wherein forming the gate structures comprises forming a bottom word line underlying the metal oxide plate and forming top word lines overlying the metal oxide plate.
19. 19 . The method of claim 15 , wherein the first source cavity, the drain cavity, and the second source cavity have substantially vertical sidewalls.
20. 20 . The method of claim 15 , further comprising forming a bit line electrically connected to the drain electrode and extending parallel to the first horizontal direction.

Description

RELATED APPLICATIONS This application is a continuation application of U.S. application Ser. No. 18/359,940 entitled “Drain Sharing for Memory Cell Thin Film Access Transistors and Methods for Forming the Same,” filed on Jul. 27, 2023, which is a divisional application of U.S. application Ser. No. 17/199,662 entitled “Drain Sharing for Memory Cell Thin Film Access Transistors and Methods for Forming the Same,” filed on Mar. 12, 2021, now issued as U.S. Pat. No. 11,856,751, the entire contents of both of which are incorporated herein by reference for all purposes. BACKGROUND Thin film transistors (TFT) made of oxide semiconductors are an attractive option for BEOL integration since TFTs may be processed at low temperatures and thus, will not damage previously fabricated devices. For example, the fabrication conditions and techniques may not damage previously fabricated FEOL devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a vertical cross-sectional view of a first exemplary structure after formation of complementary metal-oxide-semiconductor (CMOS) transistors, first metal interconnect structures formed in lower-level dielectric material layers, and an isolation dielectric layer according to an embodiment of the present disclosure. FIG. 2A is a top-down view of a portion of a memory array region of the first exemplary structure after formation of bottom gate trenches in an insulating matrix layer according to a first embodiment of the present disclosure. FIG. 2B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 2A. FIG. 2C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 2A. FIG. 3A is a top-down view of a portion of a memory array region of the first exemplary structure after formation of bottom word lines in the bottom gate trenches according to the first embodiment of the present disclosure. FIG. 3B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 3A. FIG. 3C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 3A. FIG. 3D is a vertical cross-sectional view of the first exemplary structure along the vertical plane D-D′ of FIG. 3A. FIG. 3E is a vertical cross-sectional view of the first exemplary structure along the vertical plane E-E′ of FIG. 3A. FIG. 4A is a top-down view of a portion of a memory array region of the first exemplary structure after formation of a continuous bottom gate dielectric layer, a continuous semiconducting metal oxide layer, and a continuous top gate dielectric layer according to the first embodiment of the present disclosure. FIG. 4B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 4A. FIG. 4C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 4A. FIG. 4D is a vertical cross-sectional view of the first exemplary structure along the vertical plane D-D′ of FIG. 4A. FIG. 4E is a vertical cross-sectional view of the first exemplary structure along the vertical plane E-E′ of FIG. 4A. FIG. 5A is a top-down view of a portion of a memory array region of the first exemplary structure after patterning the lower continuous gate dielectric layer, the continuous semiconducting metal oxide layer, and the upper continuous gate dielectric layer into stacks of a bottom gate dielectric layer, a semiconducting metal oxide plate, and a top gate dielectric layer according to the first embodiment of the present disclosure. FIG. 5B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 5A. FIG. 5C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 5A. FIG. 5D is a vertical cross-sectional view of the first exemplary structure along the vertical plane D-D′ of FIG. 5A. FIG. 5E is a vertical cross-sectional view of the first exemplary structure along the vertical plane E-E′ of FIG. 5A. FIG. 6A is a top-down view of a portion of a memory array region of the first exemplary structure after patterning top gate dielectric layers into multiple top gate dielectrics according to the first embodiment of the present disclosure. FIG. 6B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B′ of FIG. 6A. FIG. 6C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C′ of FIG. 6A. FIG. 6D is a vertical cross-sectional view of the first exe