US-20260129838-A1 - MEMORY DEVICE INCLUDING GATE CAPPING LAYER

Abstract

According to an embodiment of the present disclosure, a memory device may include a substrate including an active area; a word line embedded in the substrate, and crossing the active area; a gate insulating layer surrounding a side surface and a lower surface of the word line; a gate capping layer disposed on inner side surfaces of the gate insulating layer on the word line; and a bit line contact contacting the active area that is disposed between word lines, and having a side surface that faces the gate capping layer and is concave toward a center of the bit line contact.

Inventors

• Sung Soo Kim
• Na Hye WON
• Seung Hee Kim

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260507

Application Date

20250514

Priority Date

20241104

Claims (19)

1. 1 . A memory device comprising: a substrate including an active area; a word line embedded in the substrate, the word line crossing the active area; a gate insulating layer surrounding a side surface and a lower surface of the word line; a gate capping layer disposed on inner side surfaces of the gate insulating layer; and a bit line contact contacting the active area that is disposed between word lines, the bit line contact having a side surface that faces the gate capping layer and is concave toward a center of the bit line contact.
2. 2 . The memory device according to claim 1 , further comprising: a buffer layer disposed on the gate capping layer, wherein the buffer layer contacts an upper surface of the word line.
3. 3 . The memory device according to claim 1 , wherein the gate capping layer covers an entirety of the upper surface of the word line.
4. 4 . The memory device according to claim 3 , further comprising: a buffer layer disposed on the gate capping layer, wherein a lowermost surface of the buffer layer contacts the gate capping layer in an area between inner side surfaces of the gate capping layer.
5. 5 . The memory device according to claim 4 , further comprising: a spacer surrounding the side surface of the bit line contact, wherein an outer side surface of the spacer contacts the buffer layer and the gate capping layer.
6. 6 . The memory device according to claim 5 , wherein the lowermost surface of the buffer layer is located at a level lower than a lower surface of the bit line contact.
7. 7 . The memory device according to claim 1 , wherein the bit line contact includes a first section and a second section that is located on the first section and is continuous to the first section, and an angle between a side surface of the first section and an upper surface of the substrate is different from an angle between a side surface of the second section and the upper surface of the substrate.
8. 8 . The memory device according to claim 1 , wherein the bit line contact includes a first section and a second section that is located on the first section and is continuous to the first section, and wherein the area of an upper surface of the first section is smaller than the area of a lower surface of the second section.
9. 9 . The memory device according to claim 1 , wherein the gate capping layer includes nitride, and the buffer layer includes oxide.
10. 10 . A memory device comprising: a substrate including an active area; a word line embedded in the substrate, and crossing the active area; a gate insulating layer surrounding a side surface and a lower surface of the word line; a gate capping layer disposed on inner side surfaces of the gate insulating layer on the word line; a buffer layer disposed on the gate capping layer; and a bit line contact including a first section that contacts the active area between word lines and a second section that is located on the first section and is continuous to the first section, wherein an angle formed by a side surface of the first section with an upper surface of the substrate is different from an angle formed by a side surface of the second section with the upper surface of the substrate.
11. 11 . The memory device according to claim 10 , wherein a side surface of the bit line contact is concave toward a center of the bit line contact.
12. 12 . The memory device according to claim 11 , wherein the buffer layer contacts an upper surface of the word line.
13. 13 . The memory device according to claim 11 , wherein the buffer layer fills a space between inner side surfaces of the gate capping layer.
14. 14 . The memory device according to claim 11 , wherein the gate capping layer covers entirety of the upper surface of the word line.
15. 15 . The memory device according to claim 11 , wherein an angle between the side surface of the first section and the upper surface of the substrate is greater than an angle between the side surface of the second section and the upper surface of the substrate.
16. 16 . The memory device according to claim 11 , wherein the area of an upper surface of the first section is smaller than the area of a lower surface of the second section.
17. 17 . A memory device comprising: a substrate including an active area; a bit line contact contacting the active area, having a side surface that is concave toward a center of the bit line contact, and including a first section and a second section that is located on the first section and is continuous to the first section; a gate capping layer located on a side surface of the first section of the bit line contact; and a buffer layer located on a side surface of the second section of the bit line contact.
18. 18 . The memory device according to claim 17 , further comprising: a word line embedded in the substrate, and crossing the active area; and a gate insulating layer surrounding a side surface and a lower surface of the word line, wherein the gate capping layer is disposed on inner side surfaces of the gate insulating layer.
19. 19 . The memory device according to claim 17 , wherein the buffer layer fills a space between inner side surfaces of the gate capping layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2024-0153982 filed on Nov. 4, 2024, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field An embodiment of the present disclosure relates generally to a memory device, and more particularly, to a memory device including a gate capping layer. 2. Related Art Memory devices are attracting significant interest as an important element in the electronics industry thanks to their characteristics such as miniaturization, multifunctionality and low manufacturing costs. As the electronics industry has developed rapidly, memory devices are becoming increasingly highly integrated. In order for high integration of memory devices, the line width of wirings included in the memory devices is gradually decreasing and the size of memory cells is becoming smaller. Due to this fact, the difficulty of a process for forming the memory cells is increasing. SUMMARY Various embodiments of the present disclosure are directed to a memory device capable of preventing a process defect from occurring during the manufacturing process of the memory device. According to an embodiment of the present disclosure, a memory device may include a substrate including an active area; a word line embedded in the substrate, and crossing the active area; a gate insulating layer surrounding a side surface and a lower surface of the word line; a gate capping layer disposed on inner side surfaces of the gate insulating layer on the word line; and a bit line contact contacting the active area that is disposed between word lines, and having a side surface that faces the gate capping layer and is concave toward a center of the bit line contact. According to an embodiment of the present disclosure, a memory device may include a substrate including an active area; a word line embedded in the substrate, and crossing the active area; a gate insulating layer surrounding a side surface and a lower surface of the word line; a gate capping layer disposed on inner side surfaces of the gate insulating layer on the word line; a buffer layer disposed on the gate capping layer; and a bit line contact including a first section that contacts the active area between word lines and a second section that is located on the first section and is continuous to the first section, wherein an angle formed by a side surface of the first section with an upper surface of the substrate is different from an angle formed by a side surface of the second section with the upper surface of the substrate. According to an embodiment of the present disclosure, a memory device may include a substrate including an active area; a bit line contact contacting the active area, having a side surface that is concave toward a center of the bit line contact, and including a first section and a second section that is located on the first section and is continuous to the first section; a gate capping layer located on a side surface of the first section of the bit line contact; and a buffer layer located on a side surface of the second section of the bit line contact. According to an embodiment of the present disclosure, it is possible to prevent a process defect from occurring during the manufacturing process of a memory device. These and other features and advantages of the embodiments of the present disclosure will become better understood from the following embodiments in conjunction with the following description. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view illustrating a planar structure of a memory device according to an embodiment of the present disclosure. FIG. 2 is a view illustrating a cross-sectional structure taken along line I-I′ of FIG. 1. FIG. 3A is an enlarged view of a part 10 of FIG. 2. FIG. 3B is another enlarged view of the part 10 of FIG. 2. FIG. 4 is a view illustrating a cross-sectional structure taken along line II-II′ of FIG. 1. FIG. 5 is a view illustrating a cross-sectional structure taken along line III-III′ of FIG. 1. FIG. 6 is a view illustrating another cross-sectional structure taken along line I-I′ of FIG. 1. FIG. 7A is an enlarged view of a part 20 of FIG. 6. FIG. 7B is another enlarged view of the part 20 of FIG. 6. FIG. 8 is a view illustrating another cross-sectional structure of the part indicated by the line II-II′ of FIG. 1. FIG. 9 is a view illustrating another cross-sectional structure of the part indicated by the line III-III′ of FIG. 1. FIG. 10 to FIG. 16 are views illustrating a method for forming a memory device according to an embodiment of the present disclosure. FIG. 17 to FIG. 20 are views illustrating another method for forming a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of embodi