US-20260129839-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

US20260129839A1US 20260129839 A1US20260129839 A1US 20260129839A1US-20260129839-A1

Abstract

A semiconductor device with improved Gate-Induced Drain Leakage (GIDL) and a method for fabricating the same are provided. The semiconductor device includes a trench formed in a substrate; a first gate dielectric layer suitable for covering a bottom surface and sidewalls of the trench; a first buried conductive layer suitable for filling a bottom portion of the trench over the first gate dielectric layer; a second buried conductive layer including a conductive metal oxide over the first buried conductive layer; and a second gate dielectric layer disposed between the second buried conductive layer and the first gate dielectric layer.

Inventors

Sung Hwan Hwang

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20250530
Priority Date: 20241104

Claims (11)

1 . A semiconductor device comprising: a trench formed in a substrate; a first gate dielectric layer covering a bottom surface and sidewalls of the trench; a first buried conductive layer filling a bottom portion of the trench over the first gate dielectric layer; a second buried conductive layer including a conductive metal oxide over the first buried conductive layer; and a second gate dielectric layer disposed between the second buried conductive layer and the first gate dielectric layer.
2 . The semiconductor device of claim 1 , wherein the first buried conductive layer includes a metal or a metal nitride.
3 . The semiconductor device of claim 1 , wherein the second buried conductive layer includes a stacked structure of a conductive metal oxide, a metal nitride, and polysilicon, or a stacked structure of a conductive metal oxide, a metal, and polysilicon.
4 . The semiconductor device of claim 1 , wherein the conductive metal oxide includes the same metal as the first buried conductive layer.
5 . The semiconductor device of claim 1 , wherein the first buried conductive layer includes titanium nitride.
6 . The semiconductor device of claim 1 , wherein the conductive metal oxide includes titanium oxide.
7 . The semiconductor device of claim 1 , wherein the second gate dielectric layer includes silicon oxide.
8 . The semiconductor device of claim 1 , further comprising: a fin region below the first buried conductive layer, wherein an upper surface and sidewalls of the fin region are covered by the first gate dielectric layer.
9 . The semiconductor device of claim 1 , further comprising a gate capping layer suitable for filling the remaining portion of the trench over the second buried conductive layer.
10 . The semiconductor device of claim 1 , further comprising first and second conductive regions in the substrate on both sides of the trench.
11 . The semiconductor device of claim 1 , wherein the substrate includes a plurality of active regions that are spaced apart from each other, and wherein the trench is disposed in each of the active regions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2024-0154258, filed on Nov. 4, 2024, which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Embodiments of the present disclosure relate generally to a semiconductor device and a fabrication method thereof, and, more particularly, to a semiconductor device including a buried gate, and a method for fabricating the semiconductor device. 2. Description of the Related Art Metal gate electrodes are used to achieve high-performance transistors. For buried gate-type transistors, it is crucial to control the threshold voltage for optimal performance. Additionally, the Gate-Induced Drain Leakage (GIDL) characteristics significantly impact the performance of these transistors. However, as semiconductor devices become more integrated, improving GIDL characteristics becomes increasingly challenging. SUMMARY Embodiments of the present disclosure are directed to a semiconductor device with improved Gate-Induced Drain Leakage (GIDL), and a method for fabricating the semiconductor device. In accordance with an embodiment of the present disclosure, a semiconductor device includes a trench formed in a substrate; a first gate dielectric layer suitable for covering a bottom surface and sidewalls of the trench; a first buried conductive layer suitable for filling a bottom portion of the trench over the first gate dielectric layer; a second buried conductive layer including a conductive metal oxide over the first buried conductive layer; and a second gate dielectric layer disposed between the second buried conductive layer and the first gate dielectric layer. In accordance with another embodiment of the present disclosure, a method for fabricating a semiconductor device includes forming a trench in a substrate; forming a first gate dielectric layer suitable for covering a bottom surface and sidewalls of the trench; forming a first buried conductive layer suitable for filling a bottom portion of the trench over the first gate dielectric layer; forming a dielectric oxide layer over the first buried conductive layer and the first gate dielectric layer; forming a second buried conductive layer over the dielectric oxide layer; and performing an annealing process to replace the dielectric oxide layer interposed between the first buried conductive layer and the second buried conductive layer with a conductive metal oxide, and to form the dielectric oxide layer interposed between the first gate dielectric layer and the second buried conductive layer as a second gate dielectric layer. In accordance with another embodiment of the present disclosure, a semiconductor device includes a trench formed in a substrate; a first gate dielectric layer suitable for covering a bottom surface and sidewalls of the trench; a buried conductive layer including a conductive metal oxide in an upper portion of the first gate dielectric layer; and a second gate dielectric layer suitable for covering a portion of the first gate dielectric layer between the buried conductive layer and the first gate dielectric layer. In accordance with another embodiment of the present disclosure, a semiconductor device includes a trench formed in a substrate; a first gate dielectric layer suitable for covering a bottom surface and sidewalls of the trench; a first buried conductive layer suitable for filling a bottom portion of the trench over the first gate dielectric layer; a conductive metal oxide electrode disposed in an upper portion of the first buried conductive layer, wherein the line width of the bottom surface of the conductive metal oxide electrode is wider than the line width of the top surface; a second buried conductive layer in an upper portion of the metal oxide electrode; and a second gate dielectric layer disposed between the metal oxide electrode and the second buried conductive layer and the first gate dielectric layer. These and other features and advantages of the embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a plan view illustrating a semiconductor device in accordance with an embodiment of the present disclosure. FIGS. 1B and 1C are cross-sectional views illustrating the semiconductor device in accordance with an embodiment of the present disclosure. FIGS. 2A to 2G are process cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with an embodiment of the present disclosure. FIGS. 3A to 3G are process cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present disclosure. FIGS. 4A to 4H are process cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with yet another e