US-20260129840-A1 - STAGGERED BIT LINES FOR ADVANCED DRAM

Abstract

The present technology includes vertical cell dynamic random-access memory (DRAM) structures with improve bit line capacitance. Structures include a plurality of lower bit lines arranged in a first horizontal direction in a first horizontal plane. Structures include a plurality of upper bit lines arranged in the first horizontal direction in a second horizontal plane, where the first horizontal plane is vertically spaced apart from the second horizontal plane. Structures include one or more word lines arranged in a second horizontal direction. Structures include one or more channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the plurality of lower bit lines and plurality of upper bit lines intersect with a source/drain region of the one or more channels, and the one or more word lines intersect with a gated region of the one or more channels.

Inventors

• Zhijun CHEN
• Fredrick Fishburn
• Raghuveer S. MAKALA

Assignees

• APPLIED MATERIALS, INC.

Dates

Publication Date

20260507

Application Date

20241106

Claims (20)

1. 1 . A vertical cell dynamic random-access memory (DRAM) structure, comprising: one or more lower bit lines arranged in a first horizontal direction in a first horizontal plane; one or more upper bit lines arranged in the first horizontal direction in a second horizontal plane, wherein the first horizontal plane is vertically spaced apart from the second horizontal plane; one or more word lines arranged in a second horizontal direction; and a plurality of memory cell transistors each having a source/drain region and a channel extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction, such that the one or more lower bit lines or the one or more upper bit lines electrically connects to the source/drain region of a respective transistor of each transistor of the plurality of memory cell transistors, and the one or more word lines intersects with the channel of a respective transistor of the plurality of memory cell transistors.
2. 2 . The structure of claim 1 , wherein the plurality of memory cell transistors are arranged in a plurality of rows.
3. 3 . The structure of claim 2 , wherein the one or more lower bit lines electrically connect with one or more transistors in two or more spaced apart first rows of the plurality of rows, the two or more first rows being spaced apart in the first horizontal direction.
4. 4 . The structure of claim 3 , wherein the one or more upper bit lines contact one or more transistors in two or more spaced apart second rows of the plurality of rows, the two or more second rows being spaced apart in the first horizontal direction.
5. 5 . The structure of claim 4 , wherein a respective one of the first rows of the plurality of rows is disposed between two of the second rows of the plurality of rows.
6. 6 . The structure of claim 2 , wherein the one or more lower bit lines comprise a first portion of lower bit lines and a second portion of lower bit lines, wherein the first portion of lower bit lines extends along first rows of the plurality of rows, and the second portion of lower bit lines extends along second rows of the plurality of rows.
7. 7 . The structure of claim 6 , wherein the one or more upper bit lines comprise a first portion of upper bit lines and a second portion of upper bit lines, wherein the first portion of upper bit lines extends along second rows of the plurality of rows, and the second portion of upper bit lines extends along first rows of the plurality of rows.
8. 8 . The structure of claim 7 , further comprising an interconnect extending between a bit line of the first portion of lower bit lines and a bit line of the second portion of upper bit lines.
9. 9 . The structure of claim 8 , further comprising an interconnect extending between a bit line of the first portion of upper bit lines and a bit line of the second portion of lower bit lines.
10. 10 . The structure of claim 2 , wherein at least one of the one or more word lines is shared between adjacent cell transistors.
11. 11 . A method of forming a vertical cell dynamic random-access memory (DRAM) structure, comprising: forming one or more first bit line contacts to at least a first portion of cell transistors of a plurality of cell transistors; depositing one or more lower bit lines arranged in a first horizontal direction connected to the one or more first bit line contacts; depositing an isolation material over the one or more lower bit lines; forming one or more second bit line contacts to at least a second portion of cell transistors, wherein each cell transistor of the at least a second portion of the cell transistors is disposed between cell transistors of the first portion of cell transistors; and forming one or more of upper bit lines over the isolation material connected to the one or more second bit line contacts.
12. 12 . The method of claim 11 , wherein the one or more first bit line contacts are in contact with each cell transistor of the plurality of cell transistors.
13. 13 . The method of claim 11 , wherein the one or more first bit line contacts are in contact with cell transistors in spaced apart rows of the plurality of cell transistors.
14. 14 . The method of claim 11 , wherein forming the one or more lower bit lines comprises forming a first portion of lower bit lines in a first portion of rows and a second portion of lower bit lines in a second portion of rows, wherein each row of the second portion of rows is disposed between rows of the first portion of rows.
15. 15 . The method of claim 14 , wherein at least a portion of the one or more second bit line contacts is formed to the second portion of lower bit lines.
16. 16 . The method of claim 15 , wherein forming the one or more upper bit lines comprise forming a first portion of upper bit lines in the second portion of rows and a second portion of upper bit lines in the first portion of rows, wherein each row of the second portion of rows is disposed between rows of the first portion of rows.
17. 17 . The method of claim 16 , further comprising forming one or more interconnects between a bit line of the second portion of upper bit lines to a bit line of the first portion of lower bit lines.
18. 18 . The method of claim 13 , wherein forming one or more second bit line contacts to the second portion of the cell transistors comprising forming one or more junctions.
19. 19 . A semiconductor processing system, comprising: a system controller configured to form one or more first bit line contacts to at least a first portion of cell transistors of a plurality of cell transistors, in a first processing chamber; deposit one or more lower bit lines arranged in a first horizontal direction connected to the one or more first bit line contacts; deposit an isolation material over the one or more lower bit lines; form one or more second bit line contacts to at least a second portion of cell transistors, wherein each cell transistor of the at least a second portion of cell transistors is disposed between cell transistors of the first portion of cell transistors; and form one or more upper bit lines over the isolation material connected to the one or more second bit line contacts.
20. 20 . The semiconductor processing system of claim 19 , wherein a second processing chamber, a third processing chamber, and an optional fourth processing chamber, are contained within a cluster tool having a shared vacuum environment; and wherein the system is configured to perform one or more operations in the second processing chamber or third processing chamber.

Description

TECHNICAL FIELD This disclosure generally describes designs for advanced memory devices, such as 4F2 dynamic random-access memory (DRAM), 3D DRAM, and other advanced memory devices. More specifically, this disclosure describes advanced memory arrays with improved bit line capacitance. BACKGROUND With advances in computing technology, computing devices are smaller and have increased processing power. Accordingly, increased storage and memory is needed to meet the devices' programming and computing needs. The shrinking size of the devices with increased storage capacity is achieved by increasing the number of storage units having smaller geometries. Dynamic random-access memory (DRAM) architectures continue to scale down over time. For example, a one transistor, one capacitor (1T-1C) DRAM cell architecture has successfully scaled down from an 8F2 size to a 6F2 size (where F is the minimum feature size). Further design scheme changes from 6F2 to 4F2 may help further improve area density. As devices continue to scale down, there is a desire to improve the capacitance of the device. However, advanced design schemes exhibit increased bit line parasitic capacitance, as the bit line sensing margin also decreases with decreasing cell size. Thus, there is a need in the industry to improve one or more features of advanced memory devices. BRIEF SUMMARY The present technology is generally directed to vertical cell dynamic random-access memory (DRAM) structures. Structures include one or more lower bit lines arranged in a first horizontal direction in a first horizontal plane. Structures include one or more upper bit lines arranged in the first horizontal direction in a second horizontal plane, where the first horizontal plane is vertically spaced apart from the second horizontal plane. Structures include one or more word lines arranged in a second horizontal direction. Structures include a plurality of memory cell transistors each having a source/drain region and a channel extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction, such that the one or more lower bit lines and or the one or more upper bit lines electrically connects to the source/drain region of a respective transistor of each transistor of the plurality of memory cell transistors, and the one or more word lines intersects with the channel of a respective transistor of the plurality of memory cell transistors. In embodiments, structures include a plurality of cell transistors arranged in a plurality of rows. In more embodiments, the one or more lower bit lines contact one or more transistors in two or more spaced apart first rows of the plurality of rows, spaced apart in the first horizontal direction. Embodiments include where the one or more lower bit lines contact one or more cell transistors in two or more spaced apart second rows of the plurality of rows, spaced apart in the first horizontal direction. Furthermore, in embodiments, a respective one of the first rows of the plurality of rows is disposed between two of the second rows of the plurality of rows. Additionally or alternatively, in embodiments, the one or more lower bit lines include a first portion of lower bit lines and a second portion of lower bit lines, where the first portion of lower bit lines extends along first rows of the plurality of rows, and the second portion of lower bit lines extends along second rows of the plurality of rows. Moreover, in embodiments, the one or more upper bit lines include a first portion of upper bit lines and a second portion of upper bit lines, wherein the first portion of upper bit lines extends along second rows of the plurality of rows, and the second portion of upper bit lines extends along first rows of the plurality of rows. In embodiments, structures include an interconnect extending between a bit line of the first portion of lower bit lines and a bit line of the second portion of upper bit lines. In further embodiments, structures include an interconnect extending between a bit line of the first portion of upper bit lines and a bit line of the second portion of lower bit lines. Further, in embodiments, at least one of the one or more word lines is shared between adjacent cell transistors. The present technology is also generally directed to methods of forming vertical cell dynamic random-access memory (DRAM) structures. Methods include forming one or more first bit line contacts to at least a first portion of cell transistors of a plurality of cell transistors. Methods include depositing one or more lower bit lines arranged in a first horizontal direction connected to at least a first portion of the cell transistors. Methods include depositing an isolation material over the one or more lower bit lines. Methods include forming one or more second bit line contacts to at least a second portion of cell transistors, where each cell transistor of the at least a second portion o