US-20260129841-A1 - SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

US20260129841A1US 20260129841 A1US20260129841 A1US 20260129841A1US-20260129841-A1

Abstract

A semiconductor device includes: a substrate; transistors on the substrate, a channel region being between adjacent transistors, the transistor including a surrounding gate layer, a source layer, a drain layer, and a body contact layer, a body contact cavity being between the source layer and the drain layer, and the body contact layer being in the body contact cavity; a bit line at a bottom of the channel region and coupled to the transistor; a word line on a dielectric layer of the channel region and perpendicular to the bit line, wherein the dielectric layer covers the substrate and the bit line; and a base line in the body contact cavity and the channel region, wherein the base line is in contact with the body contact layer and isolated from the source layer, the drain layer, and the word line, and the base line is parallel to the bit line.

Inventors

Huilong Zhu
Xianyu Chen
Yongkui Zhang
Qi Wang
Jun Luo
Tianchun Ye

Assignees

Institute of Microelectronics, Chinese Academy of Sciences

Dates

Publication Date: 20260507
Application Date: 20241210
Priority Date: 20241101

Claims (10)

1 . A semiconductor device, comprising: a substrate; a plurality of transistors on the substrate, wherein a channel region is between adjacent transistors among the plurality of transistors, each of the plurality of transistors comprises a surrounding gate layer, a source layer, a drain layer, and a body contact layer, the surrounding gate layer is adjacent to the source layer and the drain layer, a body contact cavity is formed between the source layer and the drain layer, an opening of the body contact cavity is located on a side of the transistor away from the surrounding gate layer, and the body contact layer is located within the body contact cavity; a bit line at a bottom of the channel region and extending in a second direction, wherein the transistor is coupled to the bit line; a word line on a dielectric layer of the channel region, extending in a first direction and perpendicular to the bit line, wherein the dielectric layer covers the substrate and the bit line; and a base line in the body contact cavity and the channel region, wherein the base line is in contact with the body contact layer and isolated from the source layer, the drain layer, and the word line, and the base line extends in the second direction and is parallel to the bit line.
2 . The semiconductor device according to claim 1 , wherein each of the plurality of transistors further comprises: a channel layer on a side of the transistor away from the opening of the body contact cavity, wherein the channel layer comprises a first part, a second part, and a third part, the first part of the channel layer is connected to the body contact layer, the third part of the channel layer is connected to the source layer and the drain layer, and the second part of the channel layer is located between the first part of the channel layer and the third part of the channel layer, and wherein a doping concentration of the first part of the channel layer is greater than a doping concentration of the second part of the channel layer in a vertical direction of the semiconductor device; and wherein a height of the first part of the channel layer is greater than a height of the body contact layer in the vertical direction of the semiconductor device, and a doping type of the channel layer is same as a doping type of the source layer, the drain layer, or the body contact layer connected to the channel layer.
3 . The semiconductor device according to claim 1 , wherein the channel region extends in the second direction; and wherein widths of the plurality of transistors in the first direction are equal to each other; distances between the transistors among the plurality of transistors in the first direction are equal to each other, and distances between bit lines in the first direction are equal to each other, and the distance between the bit lines is less than 50 nm.
4 . A method of manufacturing a semiconductor device, comprising: forming a plurality of transistors arranged in a matrix on a substrate, wherein a channel region is formed between adjacent transistors among the plurality of transistors, each of the plurality of transistors comprises a surrounding gate layer, a source layer, a drain layer, and a body contact layer, the surrounding gate layer is adjacent to the source layer and the drain layer, a body contact cavity is formed between the source layer and the drain layer, an opening of the body contact cavity is located on a side of the transistor away from the surrounding gate layer, and the body contact layer is located within the body contact cavity; forming a bit line extending in a second direction at a bottom of the channel region, and depositing a dielectric layer to cover the substrate and the bit line; forming a word line extending in a first direction and perpendicular to the bit line on the dielectric layer; and forming a base line in the body contact cavity and the channel region, wherein the base line extends in the second direction and is parallel to the bit line, the base line is in contact with the body contact layer, and the base line is isolated from the source layer, the drain layer, and the word line.
5 . The method according to claim 4 , wherein forming the plurality of transistors arranged in the matrix on the substrate and forming the bit line extending in the second direction at the bottom of the channel region comprises: preparing a device precursor on the substrate, wherein the device precursor comprises a plurality of source/drain structures distributed in the first direction and a first etching sacrificial layer, a first trench or a second trench deep to the substrate is provided between adjacent source/drain structures among the plurality of source/drain structures, the first etching sacrificial layer covers the source/drain structure and fills the first trench and the second trench, each of the plurality of source/drain structures comprises the source layer, the drain layer, a body contact sacrificial layer, and the body contact layer, the body contact sacrificial layer is located between the source layer and the drain layer, the body contact layer is sandwiched in the body contact sacrificial layer, and a channel layer is formed on an inner wall of the first trench; etching the source/drain structure located on a designated side of the second trench and the first etching sacrificial layer according to a device region, and retaining a part of the source layer on the substrate as the bit line; etching a remaining part of the first etching sacrificial layer, and depositing the dielectric layer on the substrate and the bit line to form the channel region; removing the body contact sacrificial layer in the source/drain structure, so as to form the body contact cavity having the opening on a side of the source/drain structure away from the channel layer; and depositing a high dielectric constant material and a metal gate material in the body contact cavity and on a surface of the source/drain structure, and removing a part of the high dielectric constant material and a part of the metal gate material in the body contact cavity to have a predetermined width and a part of the high dielectric constant material and a part of the metal gate material on the source/drain structure close to the opening of the body contact cavity to obtain the surrounding gate layer, so as to form the transistor, wherein the body contact layer is exposed outside the surrounding gate layer.
6 . The method according to claim 5 , wherein the preparing a device precursor on the substrate comprises: sequentially growing, in a vertical direction of the semiconductor device, the source layer, a first body contact sacrificial layer, the body contact layer, a second body contact sacrificial layer, and the drain layer on the substrate, so as to form a stack; forming a patterned structure on the stack by using a patterning process, and fabricating a spacer on both sides of the patterned structure, wherein the patterned structure comprises a mandrel sacrificial layer and a second etching sacrificial layer sequentially grown; etching the stack with the spacer as a barrier, so as to form the first trench deep to the substrate; epitaxially growing the channel layer on the inner wall of the first trench; polishing the second etching sacrificial layer to expose the mandrel sacrificial layer, and removing the mandrel sacrificial layer; etching the stack with the spacer obtained after removing the mandrel sacrificial layer as a mask, so as to form the second trench deep to the substrate and the source/drain structure; and depositing the first etching sacrificial layer on the first trench, the second trench, and the source/drain structure to form the device precursor.
7 . The method according to claim 6 , wherein the epitaxially growing the channel layer on the inner wall of the first trench comprises: epitaxially growing a single crystal channel on the inner wall of the first trench; and performing a thermal annealing treatment on the single crystal channel to drive dopants in the stack into the single crystal channel, so as to form the channel layer.
8 . The method according to claim 6 , wherein an angle between the device region and the second direction is in a range of 55° to 65°; and wherein a width of the mandrel sacrificial layer in the first direction is a distance between the transistors in the first direction, a width of the transistor in the first direction is a sum of a width of the spacer in the first direction and a thickness of the channel layer in the first direction, a width of the first trench in the first direction is a sum of the width of the mandrel sacrificial layer and twice the thickness of the channel layer, and the distance between the transistors is less than 50 nm.
9 . The method according to claim 4 , wherein the forming a word line extending in a first direction and perpendicular to the bit line on the dielectric layer of the channel region comprises: sequentially depositing a high dielectric constant material and a metal gate material on the dielectric layer; and etching the high dielectric constant material and the metal gate material on the dielectric layer according to a word line region, so as to form the word line.
10 . The method according to claim 4 , wherein the forming a base line in the body contact cavity and the channel region comprises: growing an etching stop layer on the word line and the surrounding gate layer; removing a part of the etching stop layer covering the word line, so as to form a gap exposing the word line; filling the body contact cavity and the gap with an isolation layer, and keeping the body contact layer exposed outside the isolation layer; depositing a conductive material on the transistor and the channel region; and removing a part of the conductive material in contact with the transistor and a part of the conductive material covering the etching stop layer, so as to form the base line.

Description

This application claims the benefit of priority to Chinese Patent Application No. 202411554154.5, filed on Nov. 1, 2024. The entire contents of this application are hereby incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a field of semiconductor technology, and in particular, to a semiconductor device and a method of manufacturing a semiconductor device. BACKGROUND In fields of Dynamic Random Access Memory (DRAM), in the mainstream development direction, the vertical transistor structure with source, gate, and drain vertically arranged is used as the DRAM memory unit with 4F2 architecture and a high memory density, so as to improve the integration of DRAM. SUMMARY According to an aspect of the present disclosure, a semiconductor device is provided, including: a substrate; a plurality of transistors on the substrate, where a channel region is between adjacent transistors among the plurality of transistors, each of the plurality of transistors includes a surrounding gate layer, a source layer, a drain layer, and a body contact layer, the surrounding gate layer is adjacent to the source layer and the drain layer, a body contact cavity is formed between the source layer and the drain layer, an opening of the body contact cavity is located on a side of the transistor away from the surrounding gate layer, and the body contact layer is located within the body contact cavity; a bit line at a bottom of the channel region and extending in a second direction, where the transistor is coupled to the bit line; a word line on a dielectric layer of the channel region, extending in a first direction and perpendicular to the bit line, where the dielectric layer covers the substrate and the bit line; and a base line in the body contact cavity and the channel region, where the base line is in contact with the body contact layer and isolated from the source layer, the drain layer, and the word line, and the base line extends in the second direction and is parallel to the bit line. For example, each of the plurality of transistors further includes: a channel layer on a side of the transistor away from the opening of the body contact cavity, where the channel layer includes a first part, a second part, and a third part, the first part of the channel layer is connected to the body contact layer, the third part of the channel layer is connected to the source layer and the drain layer, and the second part of the channel layer is located between the first part of the channel layer and the third part of the channel layer, and where a doping concentration of the first part of the channel layer is greater than a doping concentration of the second part of the channel layer in a vertical direction of the semiconductor device. For example, a height of the first part of the channel layer is greater than a height of the body contact layer in the vertical direction of the semiconductor device, and a doping type of the channel layer is same as a doping type of the source layer, the drain layer, or the body contact layer connected to the channel layer. For example, the channel region extends in the second direction. For example, widths of the plurality of transistors in the first direction are equal to each other, distances between the transistors among the plurality of transistors in the first direction are equal to each other, and distances between bit lines in the first direction are equal to each other, and the distance between the bit lines is less than 50 nm. According to another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided, including: forming a plurality of transistors arranged in a matrix on a substrate, where a channel region is formed between adjacent transistors among the plurality of transistors, each of the plurality of transistors includes a surrounding gate layer, a source layer, a drain layer, and a body contact layer, the surrounding gate layer is adjacent to the source layer and the drain layer, a body contact cavity is formed between the source layer and the drain layer, an opening of the body contact cavity is located on a side of the transistor away from the surrounding gate layer, and the body contact layer is located within the body contact cavity; forming a bit line extending in a second direction at a bottom of the channel region, and depositing a dielectric layer to cover the substrate and the bit line; forming a word line extending in a first direction and perpendicular to the bit line on the dielectric layer; and forming a base line in the body contact cavity and the channel region, where the base line extends in the second direction and is parallel to the bit line, the base line is in contact with the body contact layer, and the base line is isolated from the source layer, the drain layer, and the word line. For example, forming the plurality of transistors arranged in the matrix on the substrate and forming the bit line extending i