US-20260129844-A1 - SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

US20260129844A1US 20260129844 A1US20260129844 A1US 20260129844A1US-20260129844-A1

Abstract

The present disclosure provides a semiconductor memory device and a method of fabricating the same, including a substrate, a plurality of bit lines, a bit line contact, a liner layer, and a storage node contact. The bit lines are separately disposed on the substrate. The bit line contact is disposed below one of the bit lines to extend into one active area. The liner layer is disposed on the substrate along an outer periphery of the bit line contact, wherein the one of the bit lines directly contacts a top surface and two sidewall of the liner layer. The storage node contact and the bit lines are alternately arranged with each other.

Inventors

Janbo Zhang

Assignees

Fujian Jinhua Integrated Circuit Co., Ltd.

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20230423

Claims (20)

1 . A semiconductor memory device, comprising: a substrate, comprising a plurality of active areas and a shallow trench isolation; a dielectric layer disposed on the substrate; a bit line, separately disposed on the dielectric layer; a bit line contact, disposed below the bit line to extend into one of the plurality of active areas; a liner layer, disposed on the substrate, along an outer periphery of the bit line contact, and being between the bit line contact and the dielectric layer, wherein the bit line directly contacts a top surface and two sidewall of the liner layer; and a storage node contact, disposed on the one of the plurality of active areas, at a side of the bit line.
2 . The semiconductor memory device according to claim 1 , wherein a portion of the liner layer is disposed between the bit line contact and the storage node contact.
3 . The semiconductor memory device according to claim 2 , further comprising a spacer disposed on a sidewall of the bit line, and a portion of the spacer is disposed on the portion.
4 . The semiconductor memory device according to claim 1 , wherein the liner layer directly contacts the shallow trench isolation in the substrate.
5 . The semiconductor memory device according to claim 2 , wherein the liner layer is disposed around the bit line contact, and comprises an insulating material which is different from that of the shallow trench isolation.
6 . The semiconductor memory device according to claim 1 , wherein each of the bit line comprises a bottom semiconductor layer, a barrier layer and a conductive layer stacked sequentially from bottom to top, and the top surface of the liner layer is higher than a top surface of the bottom semiconductor layer of each of the bit line.
7 . The semiconductor memory device according to claim 1 , wherein a portion of the liner layer is embedded in the bit line.
8 . A method of fabricating a semiconductor memory device, comprising: providing a substrate, comprising a plurality of active areas and a shallow trench isolation; forming a bit line separately disposed on the substrate; forming a bit line contact below the bit line, the bit line contact being extended into one of the plurality of active areas; forming a liner layer on the substrate along an outer periphery of the bit line contact, wherein the bit line directly contacts a top surface and two sidewall of the liner layer; and forming a storage node contact on the one of the active areas, the storage node contact and the bit line are alternately arranged with each other.
9 . The method of fabricating the semiconductor memory device according to claim 8 , wherein a portion of the liner layer is formed between the bit line contact and the storage node contact.
10 . The method of fabricating the semiconductor memory device according to claim 8 , further comprising: forming a dielectric layer on the substrate; forming a sacrificial layer on the dielectric layer, the sacrificial layer comprising an opening formed therein; forming a liner material layer on the substrate, covering the sacrificial layer and a surface of the opening; partially removing the substrate, to form a contact opening in the substrate; and partially removing the liner material layer, to form the liner layer.
11 . The method of fabricating the semiconductor memory device according to claim 10 , wherein after partially removing the dielectric layer, forming the liner material layer.
12 . The method of fabricating the semiconductor memory device according to claim 10 , wherein before partially removing the dielectric layer, forming the liner material layer.
13 . The method of fabricating the semiconductor memory device according to claim 10 , further comprising: forming a dielectric material layer on the substrate, to fill in a space between each of the bit line; partially removing the dielectric material layer, to form a plurality of plug openings, to exposed each of the plurality of active areas; and forming the storage node contacts in the plug openings.
14 . The method of fabricating the semiconductor memory device according to claim 13 , further comprising: while forming the plug openings, partially removing the liner layer between the bit line contact and the storage node contact, wherein the liner layer comprises a material the same as that of the shallow trench isolation.
15 . The method of fabricating the semiconductor memory device according to claim 9 , further comprising: forming a plurality of word lines in the substrate; and forming a plurality of word-line isolating layers on the substrate to aligned with each of the word lines, wherein the liner layer is formed between adjacent ones of the word-line isolating layer, and comprises a material the same as that of the word-line isolating layer.
16 . A semiconductor memory device, comprising: a substrate, comprising a plurality of active areas and a shallow trench isolation; a dielectric layer disposed on the substrate; a plurality of bit lines, separately disposed on the dielectric layer; a bit line contact, disposed below one of the plurality of bit lines to extend into one of the plurality of active areas; a liner layer, disposed on the substrate, being between the bit line contact and the dielectric layer, wherein a top surface of the liner layer is higher than a top surface of the dielectric layer; and a plurality of storage node contacts, each disposed on the one of the plurality of active areas, the plurality of storage node contacts and the plurality of bit lines are alternately arranged with each other, and the dielectric layer in direct contact with two side surfaces of one of the plurality of storage node contacts.
17 . The semiconductor memory device according to claim 16 , wherein a portion of the liner layer is disposed between the bit line contact and one of the plurality of storage node contacts.
18 . The semiconductor memory device according to claim 16 , further comprising: a bit line spacer, disposed on sidewall of each of the bit line, and the bit line spacer overlaying the portion of the liner layer.
19 . The semiconductor memory device according to claim 16 , wherein the liner layer directly contacts the shallow trench isolation in the substrate.
20 . The semiconductor memory device according to claim 16 , wherein the liner layer comprises an insulating material which is different from that of the shallow trench isolation.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation application of U.S. Application No. 18/241,989, filed on September 4th, 2023. The content of the application is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The present disclosure generally relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor memory device and a method of fabricating the same. 2. DESCRIPTION OF THE PRIOR ART With the trend of miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) having recessed gate structures, because the carrier channel of which is relatively long in the same semiconductor substrate compared with that of the DRAM without recessed gate structures, the leakage current from the capacitor structure in the DRAM can be reduced. Therefore, the DRAM having recessed gate structures has gradually replaced DRAM only having planar gate structures under the current mainstream development trend. Generally, the DRAM having recessed gate structures is constructed by a large number of memory cells which are arranged to form an array area, and each of the memory cells can be used to store information. Each memory cell may include a transistor element and a capacitor element connected in series, which is configured to receive voltage information from word lines (WL) and bit lines (BL). In order to satisfy the requirements of advanced products, the density of memory cells in the array area must be further increased, which increases the difficulty and complexity of related fabricating processes and designs. Therefore, the present technology needs further improvement to effectively improve the efficiency and reliability of related memory devices. SUMMARY OF THE INVENTION One of the objectives of the present disclosure provides a semiconductor memory device and a method of fabricating the same, in which a liner layer is additionally disposed at an outer periphery of the bit line contact, to shrink the diameter of the bit line contact opening, and to improve the expansion issue of the bit line contact opening caused by over-etching, and enhancing the structural reliability of the bit line contact thereby. Accordingly, the fabricating method of the present disclosure is allowable to form a semiconductor memory device with more reliable components, to effectively avoid the possible structural defects caused by continuously shrinking density of the components. To achieve the purpose described above, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, a plurality of bit lines, a bit line contact, a liner layer, and a storage node contact. The substrate includes a plurality of active areas and a shallow trench isolation. The bit lines are separately disposed on the substrate. The bit line contact is disposed below one of the bit lines to extend into one of the active areas. The liner layer is disposed on the substrate along an outer periphery of the bit line contact, wherein the one of the bit lines directly contacts a top surface and two sidewall of the liner layer. The storage node contact is disposed on the one of the active areas, and the storage node contact and the bit lines are alternately arranged with each other. To achieve the purpose described above, one embodiment of the present disclosure provides a method of fabricating a semiconductor memory device including the following steps. Firstly, a substrate is provided, and the substrate includes a plurality of active areas and a shallow trench isolation. Next, a plurality of bit lines is separately formed on the substrate. Then, a bit line contact is formed below one of the bit lines, with the bit line contact being extended into one of the active areas. After that, a liner layer is formed on the substrate along an outer periphery of the bit line contact, wherein the one of the bit lines directly contacts a top surface and two sidewall of the liner layer. Then, a storage node contact is formed on the one of the active areas, and the storage node contact and the bit lines are alternately arranged with each other. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are directed to provide a better understanding of the embodiments and are included as parts of the specification of the present disclosure. These drawings and descriptions are used to illustrate the principles of the embodiments. It should be noted that all drawings are schematic, and the relative dimensions and scales have been adjusted for the convenience of