US-20260129845-A1 - METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE INCLUDING FORMING A PRE BIT LINE CONTACT

Abstract

A method of fabricating a semiconductor device includes providing a substrate including a cell region having an active region defined by a cell element isolation, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, forming a word line structure in the substrate direction, forming a pre bit line structure on the substrate and extending from the cell region to the boundary region, the pre bit line structure including a pre first cell conductive layer and a pre second cell conductive layer sequentially stacked on the substrate, and forming a pre bit line contact between the substrate and the pre bit line structure, the pre bit line contact connecting the substrate with the pre bit line structure. The pre second cell conductive layer in the boundary region is thicker than the pre second cell conductive layer in the cell region.

Inventors

• Jin A Kim
• Kang-Uk Kim
• Sang Hoon MIN
• Choong Hyun LEE

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251229

Priority Date

20220923

Claims (20)

1. 1 . A method of fabricating a semiconductor memory device comprising: providing a substrate including a cell region having an active region defined by a cell element isolation, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, forming a word line structure in the substrate and extending in a first direction, forming a pre bit line structure on the substrate and extending from the cell region to the boundary region in a second direction that crosses the first direction, the pre bit line structure including a pre first cell conductive layer and a pre second cell conductive layer sequentially stacked on the substrate, and forming a pre bit line contact between the substrate and the pre bit line structure, the pre bit line contact connecting the substrate with the pre bit line structure, wherein the pre second cell conductive layer in the boundary region is thicker than the pre second cell conductive layer in the cell region.
2. 2 . The method of fabricating a semiconductor memory device of claim 1 , further comprising: removing the pre first cell conductive layer in the boundary region by a first thickness, and wherein the pre first cell conductive layer in the cell region is thicker than the pre first cell conductive layer in the boundary region.
3. 3 . The method of fabricating a semiconductor memory device of claim 2 , further comprising: removing the pre bit line contact by a second thickness smaller than the first thickness, and wherein in the cell region, an upper surface of the pre bit line contact is below the pre first cell conductive layer.
4. 4 . The method of fabricating a semiconductor memory device of claim 1 , wherein in the cell region, the pre second cell conductive layer on the pre bit line contact is thicker than the pre second cell conductive layer on the pre first cell conductive layer.
5. 5 . The method of fabricating a semiconductor memory device of claim 1 , wherein along the first direction, the pre bit line contact is shorter than the pre second cell conductive layer on the pre bit line contact.
6. 6 . The method of fabricating a semiconductor memory device of claim 1 , wherein, in the boundary region along the first direction, the pre first cell conductive layer is shorter than the pre second cell conductive layer.
7. 7 . The method of fabricating a semiconductor memory device of claim 1 , wherein the cell element isolation includes a first region in which the pre bit line contact is present and a second region in which the pre bit line contact is not present, and a slope of a sidewall of the pre second cell conductive layer on the first region, a slope of a sidewall of the pre second cell conductive layer on the second region, and a slope of a sidewall of the pre second cell conductive layer in the boundary region are different from one another.
8. 8 . The method of fabricating a semiconductor memory device of claim 1 , wherein the pre bit line structure further includes a pre third cell conductive layer between the pre first cell conductive layer and the pre second cell conductive layer.
9. 9 . The method of fabricating a semiconductor memory device of claim 8 , wherein along the first direction, the pre third cell conductive layer on the pre bit line contact is longer than the pre bit line contact.
10. 10 . The method of fabricating a semiconductor memory device of claim 8 , wherein, in the boundary region along the first direction, the pre third cell conductive layer is longer than the pre first cell conductive layer.
11. 11 . The method of fabricating a semiconductor memory device of claim 8 , wherein the cell element isolation includes a first region in which the pre bit line contact is present and a second region in which the pre bit line contact is not present, and a slope of a sidewall of the pre third cell conductive layer on the first region, a slope of a sidewall of the pre third cell conductive layer on the second region, and a slope of a sidewall of the pre third cell conductive layer in the boundary region are different from one another.
12. 12 . The method of fabricating a semiconductor memory device of claim 1 , further comprising: forming a bit line structure by patterning the pre bit line structure on the cell region, and forming a bit line contact connecting the substrate with the bit line structure.
13. 13 . A method of fabricating a semiconductor memory device comprising: providing a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, forming a word line structure in the substrate and extending in a first direction, forming a pre bit line structure on the substrate and extending from the cell region to the boundary region in a second direction that crosses the first direction, the pre bit line structure including a pre first cell conductive layer and a pre second cell conductive layer sequentially stacked in a direction away from the substrate, and forming a pre bit line contact between the substrate and the pre bit line structure, and the pre bit line contact electrically connecting the substrate with the pre bit line structure, wherein an upper surface of the pre first cell conductive layer in the boundary region is lower than an upper surface of the pre first cell conductive layer in the cell region, and along the first direction, the pre second cell conductive layer in the boundary region is longer than the pre second cell conductive layer in the cell region.
14. 14 . The method of fabricating a semiconductor memory device of claim 13 , wherein an upper surface of the pre bit line contact is below the pre first cell conductive layer in the cell region and is above the pre first cell conductive layer in the boundary region.
15. 15 . The method of fabricating a semiconductor memory device of claim 13 , wherein along the first direction, the pre second cell conductive layer on the pre bit line contact is longer than the pre second cell conductive layer on the pre first cell conductive layer in the cell region and is shorter than the pre second cell conductive layer in the boundary region.
16. 16 . The method of fabricating a semiconductor memory device of claim 13 , wherein the pre second cell conductive layer on the pre bit line contact is thicker than the pre second cell conductive layer on the pre first cell conductive layer in the cell region and is thinner than the pre second cell conductive layer in the boundary region.
17. 17 . The method of fabricating a semiconductor memory device of claim 13 , wherein the pre first cell conductive layer in the boundary region is thinner than the pre first cell conductive layer in the cell region.
18. 18 . The method of fabricating a semiconductor memory device of claim 13 , wherein the cell element isolation layer includes a first region in which the pre bit line contact is present and a second region in which the pre bit line contact is not present, and a slope of a sidewall of the pre second cell conductive layer in the boundary region is greater than an upper surface of a sidewall of the pre second cell conductive layer on the first region.
19. 19 . A method of fabricating a semiconductor memory device comprising: providing a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, forming a word line structure extending in the substrate in a first direction, forming a pre bit line structure extending on the substrate from the cell region to the boundary region in a second direction that crosses the first direction, the pre bit line structure including a pre first cell conductive layer, a pre second cell conductive layer and a pre third cell conductive layer sequentially stacked on the substrate, and forming a pre bit line contact between the substrate and the pre bit line structure and electrically connecting the substrate with the pre bit line structure, wherein an upper surface of the pre bit line contact is below the pre first cell conductive layer in the cell region and is higher than that of the pre first cell conductive layer in the boundary region, and the pre third cell conductive layer on the pre bit line contact is thicker than the pre third cell conductive layer on the pre first cell conductive layer in the cell region and is thinner than the pre third cell conductive layer in the boundary region.
20. 20 . The method of fabricating a semiconductor memory device of claim 19 , wherein a slope of a sidewall of the pre third cell conductive layer on the pre bit line contact is greater than that of a sidewall of the pre third cell conductive layer on the pre first cell conductive layer and is less than that of a sidewall of the pre third cell conductive layer in the boundary region.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. application Ser. No. 18/352,528, filed Jul. 14, 2023, which claims priority from Korean Patent Application No.10-2022-0120712 filed on Sep. 23, 2022 in the Korean Intellectual Property Office and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of each of which in its entirety are herein incorporated by reference. BACKGROUND Various example embodiments relate to a semiconductor memory device. As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming finer so as to implement more semiconductor devices in the same area. That is, with the increase in the degree of integration of the semiconductor device, the design rule for components of the semiconductor device has been reduced. In highly scaled semiconductor devices, a process of forming a plurality of wiring lines and a plurality of contacts interposed between the wiring lines has become increasingly complex and difficult. SUMMARY Various example embodiments provide a semiconductor memory device that may improve reliability and/or performance. Various objects and/or improvements of example embodiments are not limited to those mentioned above and additional features, which are not mentioned herein, will be clearly understood by those of ordinary skill in the art from the following description. A semiconductor memory device according to some example embodiments comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, a word line structure extending in the substrate in a first direction, a bit line structure extending on the substrate from the cell region to the boundary region in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and connecting the substrate with the bit line structure. The second cell conductive layer in the boundary region is thicker than the second cell conductive layer in the cell region. Alternatively or additionally, a semiconductor memory device according to various example embodiments comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, a word line structure extending in the substrate in a first direction, a bit line structure extending on the substrate from the cell region to the boundary region on the substrate in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked in a direction away from the substrate, and a bit line contact between the substrate and the bit line structure and electrically connecting the substrate with the bit line structure. An upper surface of the first cell conductive layer in the boundary region is lower than that of the first cell conductive layer in the cell region, and a length along the first direction of the second cell conductive layer in the boundary region is longer than a length along the first direction of the second cell conductive layer in the cell region. Alternatively or additionally, a semiconductor memory device according to various example embodiments comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region, a word line structure extending in the substrate in a first direction in the substrate, a bit line structure extending on the substrate from the cell region to the boundary region in a second direction that crosses the first direction, including first to third cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and electrically connecting the substrate with the bit line structure. An upper surface of the bit line contact is lower than an upper surface of the first cell conductive layer in the cell region and is higher than an upper surface of the first cell conductive layer in the boundary region, and the third cell conductive layer on the bit line contact is thicker than the third cell conductive layer on the first cell conductive layer in the cell region and is thinner than the third cell conductive layer in the boundary region. These and other details of the additional and/or other example embodiments are included in the detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects and features will become more apparent by describing in detail exemplary embodiments thereof with reference