US-20260129847-A1 - SEMICONDUCTOR DEVICE

Abstract

Provided is a semiconductor device including a substrate having an active region formed thereon, a gate stack on the active region, a circuit wiring disposed above the gate stack, and a contact via structure located on a side surface of the gate stack located between the active region and the circuit wiring, wherein the contact via structure includes a gate contact via extending between the circuit wiring and the active region, a first contact insulating film covering a portion of the side surface of the gate contact via and exposing a remaining portion of the side surface, and a second contact insulating film covering a portion of a side surface of the first contact insulating film and exposing a remaining portion of the side surface, and exposing a remaining portion of the side surface of the gate contact via.

Inventors

• Hongsik SHIN
• Gyeonghwan Noh
• YOUNGSIK SEO
• Seongho Yoo
• Ji-Hye Lee
• Hyunchul Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250627

Priority Date

20241106

Claims (20)

1. 1 . A semiconductor device, comprising: a substrate having an active region formed thereon; a gate stack on the active region; a circuit wiring disposed above the gate stack; and a contact via structure located on a side surface of the gate stack in a first direction parallel to an upper surface of the active region and located between the active region and the circuit wiring, wherein the contact via structure includes: a gate contact via extending in a third direction perpendicular to the upper surface of the active region between the circuit wiring and the active region; a first contact insulating film covering a portion of the side surface of the gate contact via and exposing a remaining portion of the side surface of the gate contact via; and a second contact insulating film covering a portion of a side surface of the first contact insulating film and exposing a remaining portion of the side surface of the first contact insulating film, and exposing a remaining portion of the side surface of the gate contact via.
2. 2 . The semiconductor device of claim 1 , wherein the contact via structure has: a first portion connected to the circuit wiring and including the gate contact via, the first contact insulating film, and the second contact insulating film; a second portion connected to the active region and including the gate contact via; and a third portion located between the first portion and the second portion and including the gate contact via and the first contact insulating film, wherein the second contact insulating film does not extend into the second portion or the third portion, and the first contact insulating film does not extend into the second portion.
3. 3 . The semiconductor device of claim 2 , wherein in the first portion of the contact via structure: the first contact insulating film covers a side surface of the gate contact via; and the second contact insulating film covers a side surface of the first contact insulating film.
4. 4 . The semiconductor device of claim 2 , wherein in the third portion of the contact via structure: the first contact insulating film covers the side surface of the gate contact via; and the second contact insulating film does not cover the side surface of the first contact insulating film.
5. 5 . The semiconductor device of claim 2 , wherein in the second portion of the contact via structure: the first contact insulating film does not cover the side surface of the gate contact via; the second contact insulating film does not cover the side surface of the first contact insulating film; and the gate contact via is exposed.
6. 6 . The semiconductor device of claim 2 , wherein the second portion of the contact via structure penetrates the upper surface of the active region into the active region, and is in a contact with the active region.
7. 7 . The semiconductor device of claim 2 , wherein the semiconductor device further includes: a gate spacer located on the active region next to the gate stack in the first direction; and an interlayer insulating film located on the gate spacer and covering the gate stack.
8. 8 . The semiconductor device of claim 7 , wherein the first portion of the contact via structure penetrates through the gate spacer and the upper surface of the active region into the active region.
9. 9 . The semiconductor device of claim 7 , wherein the first contact insulating film extends in the third direction from the gate spacer to a lower surface of the circuit wiring.
10. 10 . The semiconductor device of claim 7 , wherein the gate spacer is a gate spacer structure, and the gate spacer structure includes: a first gate spacer on the side surface of the gate stack in the first direction; a second gate spacer on the side surface of the first gate spacer in the first direction; a third gate spacer covering the first gate spacer and the second gate spacer; and a fourth gate spacer under the second gate spacer and the third gate spacer.
11. 11 . The semiconductor device of claim 10 , wherein: the first contact insulating film is in contact with a first portion of the side surface of the third gate spacer in the first direction; the second contact insulating film is in contact with a second portion of the side surface of the third gate spacer in the first direction; and the second contact insulating film is in contact with a portion of the side surface of the interlayer insulating film on the third gate spacer in the first direction.
12. 12 . The semiconductor device of claim 11 , wherein the second contact insulating film extends in the third direction from the side surface of the third gate spacer in the first direction to a lower surface of the circuit wiring.
13. 13 . The semiconductor device of claim 10 , wherein the gate stack is a first gate stack, and the semiconductor device includes: a second gate stack spaced apart from the first gate stack in the first direction; a first contact via structure between the first gate stack and the second gate stack; and second contact via structures respectively located on an outer side of the first gate stack and the second gate stack in the first direction.
14. 14 . The semiconductor device of claim 13 , wherein the third portion of the first contact via structure is interposed between the third gate spacer covering the first gate stack and the third gate spacer covering the second gate stack.
15. 15 . The semiconductor device of claim 13 , wherein the third portion of the second contact via structure is interposed between the third gate spacer covering the first gate stack or the second gate stack and the interlayer insulating film.
16. 16 . A semiconductor device, comprising: a substrate having an active region formed thereon; a gate stack on the active region; a circuit wiring disposed above the gate stack; and a contact via structure located on a side surface of the gate stack in a first direction parallel to an upper surface of the active region and located between the active region and the circuit wiring, wherein the contact via structure has: a first portion connected to the circuit wiring; a second portion connected to the active region; and a third portion between the first portion and the second portion, wherein a length of the contact via structure in the first direction has a step between the first portion and the third portion, and has a step between the third portion and the second portion.
17. 17 . The semiconductor device of claim 16 , wherein a length of a lower end of the first portion in the first direction is greater than a length of an upper end of the third portion in the first direction.
18. 18 . The semiconductor device of claim 16 , wherein a length of a lower end of the third portion in the first direction is greater than a length of an upper end of the second portion in the first direction.
19. 19 . The semiconductor device of claim 16 , wherein: the third portion is located on the second portion; the first portion is located on the third portion; and the second portion, the third portion, and the first portion are sequentially stacked in a third direction perpendicular to the upper surface of the active region.
20. 20 . A semiconductor device, comprising: a substrate having an active region formed thereon; a circuit wiring formed on the substrate; a first gate stack and a second gate stack located on the active region and spaced apart from each other in a first direction parallel to an upper surface of the active region; a first contact via structure located between the first gate stack and the second gate stack and between the active region and the circuit wiring; and second contact via structures, each located on an outer side of either the first gate stack or the second gate stack in the first direction and located between the active region and the circuit wiring, wherein: the first contact via structure includes a gate contact via extending in a third direction perpendicular to an upper surface of the active region from the active region to the circuit wiring, and a first contact insulating film located on a side surface of the gate contact via; and the second contact via structure includes a gate contact via extending in the third direction from the active region to the circuit wiring, a first contact insulating film covering a portion of a side surface of the gate contact via and exposing a remaining portion of the side surface of the gate contact via, and a second contact insulating film covering a portion of the side surface of the first contact insulating film and exposing a remaining portion of the side surface of the first contact insulating film, and exposing the remaining portion of the side surface of the gate contact via.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0156450 filed in the Korean Intellectual Property Office on Nov. 6, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND The present disclosure relates to a semiconductor device. Semiconductors are materials having electrical properties between a conductor and an insulator and a semiconductor material may be a material that conducts electricity under certain conditions. Various semiconductor devices such as, for example, memory devices may be manufactured using semiconductor materials. Such semiconductor devices may be used in various electronic devices. As electronic devices become more miniaturized and highly integrated, there is a need to finely form the patterns that make up semiconductor devices. As the width of these micro-patterns gradually decreases, process difficulty increases, and the defect rate of semiconductor devices may increase. SUMMARY One aspect of the present disclosure provides a semiconductor device capable of improving resistance and performance, preventing short circuit failure with a gate stack and poor contact with an active region, and reducing contact resistance with an active region by preventing a contact via structure from having an enlarged profile or having voids. A semiconductor device according to one aspect includes a substrate having an active region formed thereon, a gate stack on the active region, a circuit wiring disposed above the gate stack, and a contact via structure located on a side surface of the gate stack in a first direction parallel to an upper surface of the active region and located between the active region and the circuit wiring, wherein the contact via structure includes a gate contact via extending in a third direction perpendicular to the upper surface of the active region between the circuit wiring and the active region, a first contact insulating film covering a portion of the side surface of the gate contact via and exposing a remaining portion of the side surface of the gate contact via, and a second contact insulating film covering a portion of a side surface of the first contact insulating film and exposing a remaining portion of the side surface of the first contact insulating film, and exposing a remaining portion of the side surface of the gate contact via. A semiconductor device according to another aspect includes a substrate having an active region formed thereon, a gate stack on the active region, a circuit wiring disposed above the gate stack, and a contact via structure located on a side surface of the gate stack in a first direction parallel to an upper surface of the active region and located between the active region and the circuit wiring, wherein the contact via structure has a first portion connected to the circuit wiring, a second portion connected to the active region, a third portion located between the first portion and the second portion, wherein a length of the contact via structure in the first direction has a step between the first portion and the third portion, and has a step between the third portion and the second portion. A semiconductor device according to another aspect includes a substrate having an active region formed thereon, a circuit wiring formed on the substrate, a first gate stack and a second gate stack located on the active region and spaced apart from each other in a first direction parallel to an upper surface of the active region, a first contact via structure located between the first gate stack and the second gate stack and between the active region and the circuit wiring, and second contact via structures, each located on an outer side of either the first gate stack or the second gate stack in the first direction and located between the active region and the circuit wiring, wherein the first contact via structure includes a gate contact via extending in a third direction perpendicular to the upper surface of the active region to the circuit wiring in the active region, and a first contact insulating film located on a side surface of the gate contact via, and the second contact via structure includes a gate contact via extending in the third direction from the active region to the circuit wiring, a first contact insulating film covering a portion of the side surface of the gate contact via and exposing a remaining portion of the side surface of the gate contact via, and a second contact insulating film covering a portion of a side surface of the first contact insulating film and exposing a remaining portion of the side surface of the first contact insulating film, and exposing a remaining portion of the side surface of the gate contact via. According to embodiments, provided is semiconductor device capable of improving resistance and performance, preventing short circuit failure with a gate stack and poor contact with an active region, and