US-20260129848-A1 - MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Abstract

A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.

Inventors

• Yanhong Wang
• Wei Liu
• Yaqin LIU
• SHIQI HUANG
• Liang Chen

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20260106

Priority Date

20230726

Claims (20)

1. 1 . A memory device, comprising: a memory array structure comprising: a transistor having a first terminal and a second terminal; a storage unit coupled to the first terminal of the transistor; and a bit line coupled to the second terminal of the transistor; a first peripheral circuit disposed at one side of the memory array structure and comprising a first side in contact with the memory array structure and a second side opposite to the first side in a first direction; and a second peripheral circuit disposed in contact with the second side of the first peripheral circuit away from the memory array structure.
2. 2 . The memory device of claim 1 , wherein the first peripheral circuit comprises a sense amplifier circuit and a word line driver circuit.
3. 3 . The memory device of claim 2 , wherein the second peripheral circuit comprises an analog circuit.
4. 4 . The memory device of claim 2 , wherein the memory array structure further comprises a first bonding contact structure, and the first peripheral circuit further comprises a second bonding contact structure; and the first bonding contact structure is in contact with the second bonding contact structure.
5. 5 . The memory device of claim 4 , wherein the sensing amplifier circuit is located in a first area and a second area, and the word line driving circuit is located a third area and a fourth area.
6. 6 . The memory device of claim 5 , wherein the first area and the second area are arranged diagonally to each other, and the third area and the fourth area are arranged diagonally to each other.
7. 7 . The memory device of claim 5 , wherein the first area and the second area are between the third area and the fourth area.
8. 8 . The memory device of claim 2 , further comprising a first contact structure extending between the first peripheral circuit and the second peripheral circuit in the first direction.
9. 9 . The memory device of claim 8 , further comprising a bonding interface between the first peripheral circuit and the second peripheral circuit, wherein the first contact structure is extending through the bonding interface.
10. 10 . The memory device of claim 8 , wherein the first contact structure is located in a fifth area and a sixth area, and the sense amplifier circuit and the word line driver circuit are between the fifth area and the sixth area.
11. 11 . The memory device of claim 1 , wherein the memory array structure comprises a pad-out structure arranged on a side of the memory array structure away from the first peripheral circuit.
12. 12 . The memory device of claim 11 , wherein the memory array structure further comprises a second contact structure extending in the first direction and coupled to the pad-out structure.
13. 13 . The memory device of claim 1 , wherein the first peripheral circuit is disposed in a first periphery substrate, the second peripheral circuit is disposed in a second periphery substrate, and a thickness of the first periphery substrate is smaller than a thickness of the second periphery substrate.
14. 14 . The memory device of claim 1 , wherein the transistor comprises a semiconductor body and a gate structure surrounding the semiconductor body.
15. 15 . A method for forming a memory device, comprising: forming a memory array structure on a first substrate, wherein the memory array structure comprises a transistor having a first terminal and a second terminal, a storage unit coupled to the first terminal of the transistor, and a bit line coupled to the second terminal of the transistor; forming a first peripheral circuit in a second substrate; forming a third substrate on the first peripheral circuit; forming a second peripheral circuit on the third substrate; and bonding the memory array structure with the second peripheral circuit.
16. 16 . The method of claim 15 , wherein forming the memory array structure on the first substrate comprises: forming the transistor on a fourth substrate having the second terminal of the transistor in contact with the fourth substrate; forming the storage unit coupled to the first terminal of the transistor; forming the first substrate on the storage unit; and removing the fourth substrate.
17. 17 . The method of claim 15 , wherein forming the third substrate on the first peripheral circuit comprises: forming a dielectric layer on the third substrate; performing an implantation operation on the third substrate; and bonding the third substrate on the first peripheral circuit, the dielectric layer being in contact with the first peripheral circuit.
18. 18 . A method for forming a memory device, comprising: forming a memory array structure on a first substrate, wherein the memory array structure comprises a transistor having a first terminal and a second terminal, a storage unit coupled to the first terminal of the transistor, and a bit line coupled to the second terminal of the transistor; forming a first peripheral circuit on a second substrate; forming a second peripheral circuit on a third substrate; bonding the first peripheral circuit with the second peripheral circuit; and bonding the memory array structure with the first peripheral circuit.
19. 19 . The method of claim 18 , wherein bonding the first peripheral circuit with the second peripheral circuit comprises: thinning the second substrate; forming a dielectric layer on a thinned second substrate; and bonding the thinned second substrate with the second peripheral circuit having the dielectric layer in contact with the second peripheral circuit.
20. 20 . The method of claim 18 , wherein bonding the first peripheral circuit with the second peripheral circuit comprises: forming a fifth substrate on the first peripheral circuit; thinning the second substrate using the fifth substrate as a support substrate; bonding a thinned second substrate with the second peripheral circuit having the thinned second substrate in contact with the second peripheral circuit; and removing the fifth substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is continuation of U.S. application Ser. No. 18/231,742, filed on Aug. 8, 2023, which claims the benefit of priorities to C.N. Application No. 202310927425.6, filed on Jul. 26, 2023, and U.S. Provisional Application No. 63/396,753, filed on Aug. 10, 2022, all of which are hereby incorporated by reference in its entireties. BACKGROUND The present disclosure relates to memory devices and fabrication methods thereof. Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array. SUMMARY In one aspect, a memory device is disclosed. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure. In some implementations, the first peripheral circuit includes a sense amplifier circuit and a word line driver circuit. In some implementations, the second peripheral circuit includes an analog circuit. In some implementations, the memory array structure includes a first surface having a pad-out structure and a second surface opposite to the first surface in the first direction in contact with the first peripheral circuit. In some implementations, the storage unit is disposed between the first surface and the vertical transistor in the first direction. In some implementations, the vertical transistor is disposed between the first surface and the storage unit in the first direction. In some implementations, the memory device further includes a first connecting structure extending between the first peripheral circuit and the second peripheral circuit in the first direction. In some implementations, the memory device further includes a second connecting structure extending in the memory array structure between the first surface and the second surface in the first direction. In some implementations, the second connecting structure is in contact with the pad-out structure. In some implementations, the first peripheral circuit is disposed in a first periphery substrate, the second peripheral circuit is disposed in a second periphery substrate, and a thickness of the first periphery substrate is smaller than a thickness of the second periphery substrate. In some implementations, the vertical transistor includes a semiconductor body extending in the first direction, and a gate structure coupled to at least one side of the semiconductor body in a second direction perpendicular to the first direction. In another aspect, a memory system is disclosed. The memory system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control the memory array structure through the first peripheral circuit. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure. In still another aspect, a memory device is disclosed. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor, and a storage unit coupled to the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in co