US-20260129850-A1 - READ-ONLY MEMORY DEVICE AND METHOD

US20260129850A1US 20260129850 A1US20260129850 A1US 20260129850A1US-20260129850-A1

Abstract

An IC device includes a first transistor including a first gate coupled to a first word line and including a first work function configuration, a first metal-like defined (MD) segment adjacent to the first gate and coupled to one of a bit line or reference line, and a second MD segment adjacent to the first gate and coupled to the other of the bit line or the reference line, and a second transistor including a second gate coupled to a second word line and including a second work function configuration different from the first work function configuration, the second MD segment adjacent to the second gate, and a third MD segment adjacent to the second gate and coupled to the one of the bit line or the reference line.

Inventors

Ji-Kuan Lee
Yao-Jen Yang
Chia-En HUANG
Ting-Wei Chiang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . An integrated circuit (IC) device comprising: a first transistor comprising: a first gate coupled to a first word line and comprising a first work function configuration; a first metal-like defined (MD) segment adjacent to the first gate and coupled to one of a bit line or a reference line; and a second MD segment adjacent to the first gate and coupled to the other of the bit line or the reference line; and a second transistor comprising: a second gate coupled to a second word line and comprising a second work function configuration different from the first work function configuration, the second MD segment adjacent to the second gate; and a third MD segment adjacent to the second gate and coupled to the one of the bit line or the reference line.
2 . The IC device of claim 1 , wherein the first transistor further comprises: a third gate adjacent to the first MD segment and coupled to the first word line; and a fourth MD segment adjacent to the third gate and coupled to the other of the bit line or the reference line, and the second transistor further comprises: a fourth gate adjacent to the third MD segment and coupled to the second word line; and a fifth MD segment adjacent to the fourth gate and coupled to the other of the bit line or the reference line.
3 . The IC device of claim 2 , further comprising: an active area extending between a first edge adjacent to the fourth MD segment and a second edge adjacent to the fifth MD segment; a fifth gate overlying the first edge; and a sixth gate overlying the second edge, wherein the first through fifth MD segments are positioned on the active area between the fifth and sixth gates.
4 . The IC device of claim 1 , further comprising: an active area; a third gate overlying the active area adjacent to the first MD segment and coupled to the reference line; and a fourth gate overlying the active area adjacent to the third MD segment and coupled to the reference line, wherein the first through third MD segments are positioned on the active area between the third and fourth gates.
5 . The IC device of claim 1 , further comprising: an active area extending between a first edge adjacent to the first MD segment and a second edge adjacent to the third MD segment; a third gate overlying the first edge; and a fourth gate overlying the second edge, wherein the first through third MD segments are positioned on the active area between the third and fourth gates.
6 . The IC device of claim 1 , further comprising: a first via structure extending between the first MD segment and the one of the bit line or the reference line; a second via structure extending between the second MD segment and the other of the bit line or the reference line; and a third via structure extending between the third MD segment and the one of the bit line or the reference line.
7 . The IC device of claim 1 , wherein each of the first and second transistors comprises: a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), or a planar transistor.
8 . A read-only memory (ROM) circuit comprising: a plurality of word lines; a plurality of bit lines; a plurality of reference lines; a plurality of ROM cells, wherein each ROM cell of the plurality of ROM cells comprises a transistor comprising: a first gate coupled to a corresponding word line of the plurality of word lines and comprising a corresponding work function configuration of a plurality of work function configurations; a first metal-like defined (MD) segment adjacent to the first gate and coupled to a corresponding bit line of the plurality of bit lines; and a second MD segment adjacent to the first gate and coupled to a corresponding reference line of the plurality of reference lines; and a sense amplifier selectively coupled to each ROM cell of the plurality of ROM cells, wherein the sense amplifier is configured to output a plurality of bits having values based on the work function configurations of the plurality of work function configurations.
9 . The ROM circuit of claim 8 , wherein a total number of the work function configurations of the plurality of work function configurations is equal to four, and a total number of bits of the plurality of bits is equal to two.
10 . The ROM circuit of claim 8 , wherein the transistor of each ROM cell of the plurality of ROM cells further comprises: a second gate coupled to the corresponding word line of the plurality of word lines; and a third MD segment adjacent to the second gate, wherein either the second gate is adjacent to the first MD segment and the third MD segment is coupled to the corresponding reference line of the plurality of reference lines, or the second gate is adjacent to the second MD segment and the third MD segment is coupled to the corresponding bit line of the plurality of bit lines.
11 . The ROM circuit of claim 8 , wherein each ROM cell of the plurality of ROM cells further comprises: a second gate adjacent to one of the first or second MD segments and coupled to the corresponding reference line of the plurality of reference lines.
12 . The ROM circuit of claim 8 , wherein each ROM cell of the plurality of ROM cells further comprises: a dummy gate adjacent to one of the first or second MD segments.
13 . The ROM circuit of claim 8 , wherein each ROM cell of the plurality of ROM cells further comprises: a first via structure extending between the first MD segment and the corresponding bit line of the plurality of bit lines; and a second via structure extending between the second MD segment and the corresponding reference line of the plurality of reference lines.
14 . The ROM circuit of claim 8 , wherein the transistor of each ROM cell of the plurality of ROM cells comprises: a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), or a planar transistor.
15 . A method of manufacturing an integrated circuit (IC) device, the method comprising: constructing a first transistor, the constructing the first transistor comprising: constructing a first gate comprising a first work function configuration; and forming first and second metal-like defined (MD) segments adjacent to the first gate; constructing a second transistor, the constructing the second transistor comprising: constructing a second gate adjacent to the second MD segment and comprising a second work function configuration different from the first work function configuration; and forming a third MD segment adjacent to the second gate; forming first through fifth via structures on the respective first through third MD segments and first and second gates; forming one of a bit line or a reference line on each of the first and third via structures and the other of the bit line or the reference line on the second via structure; and forming first and second word lines on the respective fourth and fifth via structures.
16 . The method of claim 15 , wherein the constructing the first transistor further comprises: constructing a third gate adjacent to the first MD segment; and forming a fourth MD segment adjacent to the third gate, the constructing the second transistor further comprises: constructing a fourth gate adjacent to the third MD segment; and forming a fifth MD segment adjacent to the fourth gate, the forming the first through fifth via structures further comprises forming sixth through ninth via structures on the respective fourth and fifth MD segments and third and fourth gates; the forming the other of the bit line or the reference line further comprises forming the other of the bit line or the reference line on each of the sixth and seventh via structures; and the forming the first and second word lines further comprises forming the first and second word lines on the respective eighth and ninth via structures.
17 . The method of claim 16 , wherein the forming the first through fifth MD segments comprises forming the first through fifth MD segments on an active area extending between a first edge adjacent to the fourth MD segment and a second edge adjacent to the fifth MD segment, and the method further comprises constructing fifth and sixth gates overlying the first and second edges.
18 . The method of claim 15 , wherein the forming the first through third MD segments comprises forming the first through third MD segments on an active area, and the method further comprises: constructing a third gate overlying the active area adjacent to the first MD segment; constructing a fourth gate overlying the active area adjacent to the third MD segment; and constructing electrical connections between each of the third and fourth gates and the reference line.
19 . The method of claim 15 , wherein the forming the first through third MD segments comprises forming the first through third MD segments on an active area extending between a first edge adjacent to the first MD segment and a second edge adjacent to the third MD segment, and the method further comprises constructing third and fourth gates overlying the first and second edges.
20 . The method of claim 15 , wherein the constructing the first and second transistors comprises constructing: gate-all-around (GAA) transistors, fin field-effect transistors (FinFETs), or planar transistors.

Description

BACKGROUND The ongoing trend in miniaturizing integrated circuits (ICs) has resulted in progressively smaller devices which consume less power, yet provide more functionality at higher speeds than earlier technologies. Such miniaturization has been achieved through design and manufacturing innovations tied to increasingly strict specifications. Various electronic design automation (EDA) tools are used to generate, revise, and verify designs for semiconductor devices while ensuring that IC structure design and manufacturing specifications are met. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic diagram of a memory circuit, in accordance with some embodiments. FIGS. 2A-2D are a plan view, side view, and cross-sectional views of an IC device and layout diagram, in accordance with some embodiments. FIGS. 3A-3D are a plan view, side view, and cross-sectional views of an IC device and layout diagram, in accordance with some embodiments. FIGS. 4A-4D are a plan view, side view, and cross-sectional views of an IC device and layout diagram, in accordance with some embodiments. FIG. 5A depicts memory circuit operating parameters, in accordance with some embodiments. FIGS. 5B-5D are cross-sectional views of IC structures and layout diagrams, in accordance with some embodiments. FIG. 6 is a flowchart of a method of operating a memory circuit, in accordance with some embodiments. FIG. 7 is a flowchart of a method of manufacturing an IC device, in accordance with some embodiments. FIG. 8 is a flowchart of a method of generating an IC layout diagram, in accordance with some embodiments. FIG. 9 is a block diagram of an IC layout diagram generation system, in accordance with some embodiments. FIG. 10 is a block diagram of an IC manufacturing system, and an IC manufacturing flow associated therewith, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In various embodiments, an integrated circuit (IC) device, read-only memory (ROM) circuit, and corresponding methods include a transistor having one of a predetermined number of work function configurations. The multiple work function configurations, and in some embodiments threshold voltages corresponding to the work function configurations, represent encoding levels such that a ROM circuit is capable of determining the encoding levels by detecting the work function configurations, e.g., by detecting the threshold voltages, of single IC device transistors and outputting a plurality of bits based on the encoding levels. The IC device is thereby capable of having increased coding density by providing multi-level coding in a smaller area compared to other approaches, e.g., those in which in which a single transistor location is used to represent binary encoding levels based on the presence or absence of a working transistor. Because the IC device includes a working transistor at each transistor location, the IC