US-20260129851-A1 - THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LATERAL ETCH-STOP STRUCTURES AND METHODS OF FORMING THE SAME

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers and including stepped surfaces in a staircase region, a retro-stepped dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening, and vertically-extending silicon oxycarbide material portions located between the retro-stepped dielectric material portion and the electrically conductive layers.

Inventors

• Takumi Moriyama
• Naohiro Hosoda
• Ryota Suzuki
• Masanori Tsutsumi

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . A memory device, comprising: an alternating stack of insulating layers and electrically conductive layers and comprising stepped surfaces in a staircase region; a retro-stepped dielectric material portion overlying the stepped surfaces of the alternating stack; a memory opening vertically extending through the alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of memory elements; and vertically-extending silicon oxycarbide material portions located between the retro-stepped dielectric material portion and the electrically conductive layers.
2. 2 . The memory device of claim 1 , wherein a respective one of the vertically-extending silicon oxycarbide material portions contacts a sidewall of a respective one of the electrically conductive layers.
3. 3 . The memory device of claim 2 , wherein the respective one of the vertically-extending silicon oxycarbide material portions further contacts a sidewall of a respective one of the insulating layers which underlies the respective electrically conductive layer.
4. 4 . The memory device of claim 1 , wherein the vertically-extending silicon oxycarbide material portions comprise portions of a silicon oxycarbide material layer which overlies the stepped surfaces and further comprises horizontally-extending silicon oxycarbide material portions that interconnect the vertically-extending silicon oxycarbide portions.
5. 5 . The memory device of claim 4 , wherein the silicon oxycarbide material layer continuously extends from a bottommost surface of the retro-stepped dielectric material portion to a topmost surface of the retro-stepped dielectric material portion.
6. 6 . The memory device of claim 1 , wherein the vertically-extending silicon oxycarbide material portions are laterally spaced apart from each other by horizontally-extending surface segments of the stepped surfaces.
7. 7 . The memory device of claim 1 , wherein the stepped surfaces comprise horizontally-extending surface segments of the electrically conductive layers that are spaced from the retro-stepped dielectric material portion by a respective horizontally-extending silicon oxycarbide material portion.
8. 8 . The memory device of claim 1 , wherein the stepped surfaces comprise horizontally-extending surface segments of the electrically conductive layers that are in direct contact with horizontal surface segments of the retro-stepped dielectric material portion.
9. 9 . The memory device of claim 1 , wherein each of the electrically conductive layers is vertically spaced from a respective overlying insulating layer of the insulating layers by a respective overlying silicon oxycarbide liner.
10. 10 . The memory device of claim 9 , wherein each of the electrically conductive layers is vertically spaced from a respective underlying insulating layer of the insulating layers by a respective underlying silicon oxycarbide liner.
11. 11 . The memory device of claim 9 , wherein each of the electrically conductive layers comprises a respective first top surface segment that directly contacts the respective overlying silicon oxycarbide liner.
12. 12 . The memory device of claim 9 , wherein, for each of the electrically conductive layers, the respective overlying silicon oxycarbide liner has a different thickness than the vertically-extending silicon oxycarbide material portions.
13. 13 . The memory device of claim 9 , wherein, for each of the electrically conductive layers, the respective overlying silicon oxycarbide liner has a different atomic percentage of carbon than the vertically-extending silicon oxycarbide material portions.
14. 14 . The memory device of claim 1 , wherein the vertical stack of memory elements comprises portions of the memory film located at vertical levels of the electrically conductive layers.
15. 15 . The memory device of claim 14 , wherein the memory film is thicker at vertical levels of the electrically conductive layers than at vertical levels of the insulating layers.
16. 16 . A method of forming a memory device, comprising: forming a vertical repetition of multiple instances of a repetition unit over a substrate, wherein the repetition unit comprises, from bottom to top, an insulating layer, a first silicon oxycarbide liner, a sacrificial material layer, and a second silicon oxycarbide liner; forming stepped surfaces by patterning the vertical repetition; forming vertically-extending silicon oxycarbide material portions on vertical steps of the stepped surfaces; forming a memory opening through the vertical repetition; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel; forming laterally-extending cavities by removing the sacrificial material layers selectively to the first silicon oxycarbide liners, the second silicon oxycarbide liners, and the vertically-extending silicon oxycarbide material portions; and forming electrically conductive layers in the laterally-extending cavities.
17. 17 . The method of claim 16 , further comprising depositing a silicon oxycarbide material layer on the stepped surfaces, wherein the vertically-extending silicon oxycarbide material portions comprise portions of the silicon oxycarbide material layer.
18. 18 . The method of claim 17 , further comprising forming a retro-stepped dielectric material portion over the silicon oxycarbide material layer, wherein the vertical repetition is spaced from the retro-stepped dielectric material portion by the silicon oxycarbide material layer.
19. 19 . The method of claim 17 , further comprising performing an anisotropic etch process that etches horizontally-extending portions of the silicon oxycarbide material layer, wherein horizontal surface segments of the sacrificial material layers are exposed after the anisotropic etch process.
20. 20 . The method of claim 16 , wherein the electrically conductive layers are formed directly on horizontally-extending surfaces of the first silicon oxycarbide liners and the second silicon oxycarbide liners and directly on the vertically-extending silicon oxycarbide material portions.

Description

FIELD The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device containing silicon oxycarbide lateral etch-stop structures and methods of forming the same. BACKGROUND Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High-Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. SUMMARY According to an aspect of the present disclosure, a memory device comprises: an alternating stack of insulating layers and electrically conductive layers and comprising stepped surfaces in a staircase region; a retro-stepped dielectric material portion overlying the stepped surfaces of the alternating stack; a memory opening vertically extending through the alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of memory elements; and vertically-extending silicon oxycarbide material portions located between the retro-stepped dielectric material portion and the electrically conductive layers. According to another aspect of the present disclosure, a method of forming a memory device comprises: forming a vertical repetition of multiple instances of a repetition unit over a substrate, wherein the repetition unit comprises, from bottom to top, an insulating layer, a first silicon oxycarbide liner, a sacrificial material layer, and a second silicon oxycarbide liner; forming stepped surfaces by patterning the vertical repetition; forming vertically-extending silicon oxycarbide material portions on vertical steps of the stepped surfaces; forming a memory opening through the vertical repetition; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel; forming laterally-extending cavities by removing the sacrificial material layers selectively to the first silicon oxycarbide liners, the second silicon oxycarbide liners, and the vertically-extending silicon oxycarbide material portions; and forming electrically conductive layers in the laterally-extending cavities. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic vertical cross-sectional view of a first exemplary structure after formation of optional semiconductor devices, optional lower-level metal interconnect structures, a semiconductor material layer, and a first vertical repetition of multiple instances of a repetition unit of an insulating layer, a first silicon oxycarbide and liner, a sacrificial material layer, and a second silicon oxycarbide liner according to a first embodiment of the present disclosure. FIG. 2 is a schematic vertical cross-sectional view of the first exemplary structure after formation of first stepped surfaces according to the first embodiment of the present disclosure. FIG. 3 is a schematic vertical cross-sectional view of the first exemplary structure after formation of a first silicon oxycarbide material layer according to the first embodiment of the present disclosure. FIG. 4 is a schematic vertical cross-sectional view of the first exemplary structure after formation of a first retro-stepped dielectric material portion according to the first embodiment of the present disclosure. FIG. 5 is a schematic vertical cross-sectional view of the first exemplary structure after formation of a second vertical repetition of multiple instances of the repetition unit and after formation of second stepped surfaces according to the first embodiment of the present disclosure. FIG. 6 is a schematic vertical cross-sectional view of the first exemplary structure after formation of a second silicon oxycarbide material layer according to the first embodiment of the present disclosure. FIG. 7 is a schematic vertical cross-sectional view of the first exemplary structure after formation of a second retro-stepped dielectric material portion according to the first embodiment of the present disclosure. FIG. 8A is a schematic vertical cross-sectional view of the first exemplary structure after formation of memory openings and support openings according to the first embodiment of the present disclosure. FIG. 8B is a top-down view of the first exemplary structure of FIG. 8A. The vertical plane A-A′ is the plane of the cross-section for FIG. 8A. FIG. 9A-9F are sequential schematic vertical cross-sectional views of a memory opening within the first exemplary structure during formation of a memory opening fill structure according to the first embodiment of the present disclosure. FIG. 10 is a schematic vertical cross-sectional view of the first exemplary structure after formation of memory opening fill structures and support pillar structures according to the first embodiment of the present disclosure. FIG. 11A is a schematic vertical cross-sectional