US-20260129853-A1 - SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

US20260129853A1US 20260129853 A1US20260129853 A1US 20260129853A1US-20260129853-A1

Abstract

The semiconductor device according to the present disclosure may include a peripheral circuit structure including a substrate having a first region and a second region and circuit elements on the substrate, the first region and the second region arranged in a first direction, and a cell structure on the peripheral circuit structure, the cell structure includes a mold structure including mold insulating layers and gate electrodes alternately stacked, a channel structure penetrating the mold structure in the first region, a contact structure in contact with the gate electrode in the second region, upper wires extending in a second direction intersecting the first direction, the upper wires spaced apart from each other in the first direction on the mold structure, and a marker pattern overlapping the upper wires in a third direction intersecting the first direction and the second direction.

Inventors

Byunggon PARK
Junbeom PARK
Yongjoon Shin
Soo-Sik Oh
Hyun Syek Oh
Taesu Yoon
Sooyoung Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250422
Priority Date: 20241104

Claims (20)

1 . A semiconductor device comprising: a peripheral circuit structure including a substrate having a first region and a second region and circuit elements on the substrate, the first region and the second region arranged in a first direction; and a cell structure on the peripheral circuit structure, the cell structure comprising a mold structure including mold insulating layers and gate electrodes alternately stacked; a channel structure penetrating the mold structure in the first region; a contact structure in contact with the gate electrodes in the second region; upper wires extending in a second direction intersecting the first direction; and a marker pattern overlapping the upper wires in a third direction intersecting the first direction and the second direction.
2 . The semiconductor device as claimed in claim 1 , wherein the marker pattern overlaps the upper wires in the first direction and the second direction.
3 . The semiconductor device as claimed in claim 2 , wherein an upper surface of the marker pattern is at a same level as an upper surface of the upper wires.
4 . The semiconductor device as claimed in claim 2 , wherein a width in the first direction of an upper surface of the marker pattern is larger than a width in the first direction of a lower surface of the marker pattern.
5 . The semiconductor device as claimed in claim 1 , wherein the upper wires comprise a first upper wire and a second upper wire spaced apart from the first upper wire in the first direction, and the marker pattern comprises, a first unit pattern comprising a first marker overlapping the first upper wire in the third direction and a second marker overlapping the second upper wire in the third direction, wherein the first marker and the second marker are positioned alternately in the first direction; and a second unit pattern comprising a third marker overlapping the first marker in the first direction and a fourth marker overlapping the second marker in the first direction.
6 . The semiconductor device as claimed in claim 5 , wherein the first unit pattern and the second unit pattern are repeated in the first direction or the second direction.
7 . The semiconductor device as claimed in claim 5 , wherein the marker pattern further comprises an extension marker pattern overlapping at least a portion of the first unit pattern or the second unit pattern in the first direction and in the second region.
8 . The semiconductor device as claimed in claim 7 , wherein the first unit pattern comprises a first reference marker at one end in the second direction and a second reference marker at another end, and the extension marker pattern comprises, a first extension marker overlapping the first reference marker in the first direction; a second extension marker overlapping the second reference marker in the first direction; and a third extension marker in a middle between the first extension marker and the second extension marker in the second direction.
9 . The semiconductor device as claimed in claim 1 , further comprising a plurality of word line cutting structures extending in the first direction in the first region and the second region and separating a plurality of cell blocks, wherein at least a portion of the marker pattern overlaps the plurality of word line cutting structures in the third direction.
10 . The semiconductor device as claimed in claim 5 , wherein, in a plan view, the marker pattern comprises a zigzag pattern.
11 . The semiconductor device as claimed in claim 1 , further comprising an interlayer insulating film at a higher level than the upper wires, wherein the marker pattern overlaps the interlayer insulating film in the first direction and the second direction.
12 . The semiconductor device as claimed in claim 11 , wherein the marker pattern comprises a metal material.
13 . The semiconductor device as claimed in claim 1 , wherein the peripheral circuit structure comprises a first bonding metal layer electrically connected to the channel structure, and the cell structure comprises a second bonding metal layer in contact with the first bonding metal layer.
14 . The semiconductor device as claimed in claim 13 , further comprising: a plate layer comprising a first surface facing the peripheral circuit structure and a second surface opposite to the first surface and arranged on an upper surface of the mold structure; and via structures spaced apart from each other in the first direction on the second surface of the plate layer, wherein the upper wires are on an upper surface of the via structures.
15 . A semiconductor device comprising: a peripheral circuit structure including a substrate having a first region and a second region, and circuit elements on the substrate, the first region and the second region are in a first direction; and a cell structure on the peripheral circuit structure, wherein the cell structure comprises, a mold structure including mold insulating layers and gate electrodes alternately stacked; a channel structure penetrating the mold structure in the first region; a contact structure in contact with the gate electrodes in the second region; upper wires comprising a cell upper wire in the first region and an extension upper wire in the second region, extending in a second direction intersecting the first direction, and spaced apart from each other in the first direction; and a marker pattern comprising a cell marker pattern overlapping the cell upper wire in a third direction intersecting the first direction and the second direction and an extension marker pattern overlapping the extension upper wire, and the extension marker pattern overlaps at least a portion of the cell marker pattern in the first direction.
16 . The semiconductor device as claimed in claim 15 , wherein the marker pattern overlaps the upper wires in the first direction and the second direction and comprises an insulating material.
17 . The semiconductor device as claimed in claim 16 , wherein the cell marker pattern overlaps each of the upper wires adjacent to each other among the upper wires in the second direction.
18 . The semiconductor device as claimed in claim 15 , wherein each of a plurality of markers forming the marker pattern has a length in the second direction that is longer than a length in the first direction.
19 . The semiconductor device as claimed in claim 15 , wherein a length of the extension upper wire in the first direction is longer than a length of the cell upper wire in the first direction.
20 . An electronic system comprising: a main substrate; a semiconductor device comprising a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, the cell structure comprising, a mold structure including a plurality of mold insulating layers and a plurality of gate electrodes alternately stacked, the plurality of mold insulating layers and the plurality of gate electrodes extending in a first direction; a channel structure penetrating the mold structure in a first region; a contact structure contacting the plurality of gate electrodes in a second region; upper wires comprising a cell upper wire in the first region and an extension upper wire in the second region, the upper wires extending in a second direction intersecting the first direction; and a marker pattern comprising a cell marker pattern overlapping the cell upper wire in a third direction intersecting the first direction and the second direction, and an extension marker pattern overlapping the extension upper wire, and the extension marker pattern overlaps at least a portion of the cell marker pattern in the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to and the benefit of Korean Application No. 10-2024-0154218, filed on Nov. 4, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein. BACKGROUND Technical Field The present disclosure relates to semiconductor devices and electronic systems including the same. Description of the Related Art Semiconductor devices are key components used to control or amplify electrical signals of electronic devices, and various types of semiconductor devices can be manufactured. Semiconductor devices can be manufactured by forming various microstructures on a semiconductor wafer through several unit processes, such as an etching process, a deposition process, or an ion implantation process. In addition, it is desirable to check whether defects have occurred, the location of the defects, etc. after a semiconductor device has been manufactured. In order to analyze defects in semiconductor devices, optical equipment such as electron microscopes may be used to observe the semiconductor devices. In particular, in order to quickly determine where a defect has occurred, etc., the location of the defect can be relatively determined based on some of a number of structures of a semiconductor device. SUMMARY The present disclosure has been made in an effort to provide semiconductor devices including a marker pattern that facilitates the determination of the location of defects. According to some example embodiments of the present disclosure to solve the above-mentioned technical problems, a semiconductor device includes a peripheral circuit structure including a substrate having a first region and a second region and circuit elements on the substrate, the first region and the second region arranged in a first direction, and a cell structure on the peripheral circuit structure. The cell structure includes a mold structure including mold insulating layers and gate electrodes alternately stacked, a channel structure penetrating the mold structure in the first region, a contact structure in contact with the gate electrode in the second region, upper wires extending in a second direction intersecting the first direction, and a marker pattern overlapping the upper wires in a third direction intersecting the first direction and the second direction. According to some example embodiments of the present disclosure to solve the above-mentioned technical problems, a semiconductor device includes a peripheral circuit structure including comprising a substrate having a first region and a second region arranged side by side in a first direction, and circuit elements on the substrate, the first region and the second region in a first direction, and a cell structure on the peripheral circuit structure. The cell structure includes a mold structure including mold insulating layers and gate electrodes alternately stacked; a channel structure penetrating the mold structure in the first region; a contact structure in contact with the gate electrode in the second region; an upper wire comprising a cell upper wire in the first region and an extension upper wire in the second region, extending in a second direction intersecting the first direction; and a marker pattern including a cell marker pattern overlapping the cell upper wire in a third direction intersecting the first direction and the second direction and an extension marker pattern overlapping the extension upper wire. The extension marker pattern overlaps at least a portion of the cell marker pattern in the first direction. According to some example embodiments of the present disclosure to solve the above-mentioned technical problems, an electronic system includes a main substrate, a semiconductor device including a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate. The cell structure incudes a mold structure including a plurality of mold insulating layers and a plurality of gate electrodes alternately stacked, the plurality of mold insulating layers and the plurality of gate electrodes extending in a first direction, a channel structure penetrating the mold structure in a first region; a contact structure contacting the gate electrode in a second region; upper wires including a cell upper wire in the first region and an extension upper wire in the second region, extending in a second direction intersecting the first direction, and spaced apart from each other in the first direction; and a marker pattern including a cell marker pattern overlapping the cell upper wire in a third direction intersecting the first direction and the second direction and an extension marker pattern overlapping the extension upper wire. The extension marker pattern overlaps at least a portion of the cell marker pattern in the firs