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US-20260129855-A1 - THREE-DIMENSIONAL MEMORY DEVICES WITH CHANNEL STRUCTURES HAVING PLUM BLOSSOM SHAPE

US20260129855A1US 20260129855 A1US20260129855 A1US 20260129855A1US-20260129855-A1

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel.

Inventors

  • Tingting Gao
  • Lei Xue
  • Xiaoxin LIU
  • Wanbo GENG

Assignees

  • YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date
20260507
Application Date
20251226

Claims (20)

  1. 1 . A three-dimensional (3D) memory device, comprising: a continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following a plum blossom shape from outside to inside in this order in a plan view; a plurality of separate semiconductor channels each disposed laterally over part of the continuous tunneling layer at a respective apex of the plum blossom shape; a plurality of separate petal capping layers each disposed laterally over a respective one of the plurality of semiconductor channels; and a continuous core capping layer laterally surrounded by the plurality of petal capping layers and the tunneling layer, wherein the petal capping layer and the core capping layer comprise different dielectric materials.
  2. 2 . The 3D memory device of claim 1 , wherein the blocking layer, charge trapping layer, tunneling layer, semiconductor channel, petal capping layer, and core capping layer comprise silicon oxide, silicon nitride, silicon oxide, polysilicon, silicon nitride, and silicon oxide, respectively.
  3. 3 . The 3D memory device of claim 1 , wherein a number of the semiconductor channels is greater than 2.
  4. 4 . The 3D memory device of claim 1 , wherein a thickness of each of the blocking layer, charge trapping layer, tunneling layer, and semiconductor channel is nominally uniform in the plan view.
  5. 5 . The 3D memory device of claim 1 , wherein a thickness of each of the petal capping layers is nonuniform in the plan view.
  6. 6 . The 3D memory device of claim 1 , further comprising a plurality of channel plugs each disposed above and in contact with a respective one of the plurality of semiconductor channels and a respective one of the plurality of petal capping layers.
  7. 7 . The 3D memory device of claim 6 , wherein the semiconductor channel and the channel plug comprise a same semiconductor material.
  8. 8 . The 3D memory device of claim 6 , wherein the plurality of semiconductor channels are separated from one another, and the plurality of channel plugs are separated from one another.
  9. 9 . The 3D memory device of claim 6 , wherein in the respective apex of the plum blossom shape, a lateral dimension of the channel plug is greater than a lateral dimension of the semiconductor channel.
  10. 10 . The 3D memory device of claim 6 , wherein in the respective apex of the plum blossom shape, one of the petal capping layers is coplanar with one of the semiconductor channels.
  11. 11 . The 3D memory device of claim 6 , wherein in the respective apex of the plum blossom shape, one of the channel plugs is laterally aligned with the one of the semiconductor channels and one of the petal capping layers.
  12. 12 . The 3D memory device of claim 1 , wherein the respective apex of the plum blossom shape comprises a curved shape.
  13. 13 . The 3D memory device of claim 1 , wherein the plurality of semiconductor channels are separated from one another at intersections where one apex of the plum blossom shape intersects with another apex of the plum blossom shape.
  14. 14 . The 3D memory device of claim 6 , wherein the plurality of channel plugs are separated from one another at intersections where one apex of the plum blossom shape intersects with another apex of the plum blossom shape.
  15. 15 . The 3D memory device of claim 1 , wherein a thickness of one petal capping layer of the plurality of petal capping layers, in the plan view, is reduced from a middle portion of the respective apex of the plum blossom shape to a side portion of the respective apex of the plum blossom shape.
  16. 16 . The 3D memory device of claim 6 , wherein a thickness of one channel plug of the plurality of channel plugs, in the plan view, is reduced from a middle portion of the respective apex of the plum blossom shape to a side portion of the respective apex of the plum blossom shape.
  17. 17 . The 3D memory device of claim 16 , wherein the middle portion of the respective apex of the plum blossom shape comprises a curved shape.
  18. 18 . The 3D memory device of claim 16 , wherein the side portion of the respective apex of the plum blossom shape comprises a curved shape.
  19. 19 . The 3D memory device of claim 6 , wherein one channel plug of the channel plugs is above and in contact with a corresponding petal capping layer of the plurality of petal capping layers.
  20. 20 . The 3D memory device of claim 1 , wherein four semiconductor channels of the plurality of semiconductor channels are surrounded by the continuous blocking layer, the continuous charge trapping layer, and the continuous tunneling layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. application Ser. No. 17/112,594, filed on Dec. 4, 2020, which is a continuation of International Application No. PCT/CN 2020/121810, filed on Oct. 19, 2020, both of which are hereby incorporated by reference in their entireties. This application is also related to U.S. application Ser. No. 17/112,635, filed on Dec. 4, 2020, which is hereby incorporated by reference in its entirety. BACKGROUND Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof. Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. SUMMARY Embodiments of 3D memory devices and fabrication methods thereof are disclosed herein. In one example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel. In another example, a 3D memory device includes a continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following a plum blossom shape from outside to inside in this order in a plan view. The 3D memory device also includes a plurality of separate semiconductor channels each disposed laterally over part of the continuous tunneling layer at a respective apex of the plum blossom shape, and a plurality of separate petal capping layers each disposed laterally over a respective one of the plurality of semiconductor channels. The 3D memory device further includes a continuous core capping laterally surrounded by the plurality of petal capping layers and the tunneling layer. The petal capping layer and the core capping layer include different dielectric materials. In still another example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A blocking layer, a charge trapping layer, a tunneling layer, and a semiconductor channel layer each following the plum blossom shape along sidewalls of the channel hole are sequentially formed. A protection layer is formed over the semiconductor channel layer, such that an apex thickness of the protection layer at each apex of the plum blossom shape is greater than an edge thickness of the protection layer at edges of the plum blossom shape. Parts of the protection layer that are at the edges of the plum blossom shape are oxidized. The oxidized parts of the protection layer are removed to expose parts of the semiconductor channel layer that are at the edges of the plum blossom shape, leaving a remainder of the protection layer at each apex of the plum blossom shape. The exposed parts of the semiconductor channel layer are removed to separate the semiconductor channel layer into a plurality of semiconductor channels each at a respective apex of the plum blossom shape. In yet another example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed laterally over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed. A plurality of separate channel plugs each disposed above and in contact with a respective one of the plurality of separate semiconductor channels are formed. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. FIG. 1 illustrates a plan view of a cross-section and a top perspective view of another cross-section of a 3D memory device having a circular channel structure. FIGS. 2A and 2B illustrate a top perspective view of a cross-section and plan views of cross-sectio