US-20260129856-A1 - THREE-DIMENSIONAL MEMORY AND FABRICATION METHOD FOR THE SAME

US20260129856A1US 20260129856 A1US20260129856 A1US 20260129856A1US-20260129856-A1

Abstract

The present application provides a three-dimensional memory and a fabrication method for the same. The method includes forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure, forming a selection stack structure stacked on the storage stack structure and forming a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. The width of the selection channel structure is smaller than the width of the storage channel structure on a plane parallel to the substrate and forming a TSG cut structure that penetrates the selection stack structure. The three-dimensional memory and the fabrication method for the same increases the process window for the TSG cut structure formed between the selection channel structures and improves the storage density.

Inventors

Tingting Gao
Zhiliang XIA
Xiaoxin LIU
Changzhi Sun
Xiaolong Du

Assignees

YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20260105
Priority Date: 20210621

Claims (20)

1 . A three-dimensional (3D) memory device, comprising: a storage stack structure extending in a first direction and a third direction that is perpendicular to the first direction; a storage channel structure extending through the storage stack structure in a second direction perpendicular to the first direction and the third direction; a selection stack structure disposed on the storage stack structure; a selection channel structure extending through the selection stack structure in the second direction and contacting the storage channel structure; and a TSG cut structure extending into the selection stack structure in the second direction and extending in the third direction, wherein the selection channel structure adjacent to the TSG cut structure is shifted off-axis with respect to the storage channel structure in the first direction away from the TSG cut structure to increase a distance between the TSG cut structure and the selection channel structure.
2 . The three-dimensional memory device of claim 1 , wherein the storage channel structure comprises a first end and the selection channel structure comprises a second end in contact with the first end, and a width of the first end is larger than a width of the second end in the first direction.
3 . The three-dimensional memory device of claim 2 , wherein the selection channel structure comprises a third end opposite to the second end in the second direction, and the width of the first end is larger than a width of the third end in the first direction.
4 . The three-dimensional memory device of claim 3 , wherein the width of the second end is smaller than the width of the third end in the first direction.
5 . The three-dimensional memory device of claim 3 , further comprising a selection channel plug comprising a fourth end in contact with the third end and a fifth end opposite to the fourth end, wherein the width of the third end is smaller than a width of the fifth end in the first direction.
6 . The three-dimensional memory device of claim 1 , wherein the storage channel structure comprises a channel layer and the selection channel structure comprises a conductive layer, and the channel layer and the conductive layer are both in contact with a storage channel plug.
7 . The three-dimensional memory device of claim 6 , wherein the selection channel structure further comprises a dielectric core surrounded by the conductive layer and an insulating layer between the conductive layer and the selection stack structure.
8 . The three-dimensional memory device of claim 6 , further comprising a selection channel plug in contact with the conductive layer, wherein the conductive layer is between the selection channel plug and the storage channel plug in the second direction, and the conductive layer, the storage channel plug, and the selection channel plug comprise polysilicon.
9 . The three-dimensional memory device of claim 1 , wherein the TSG cut structure is a wave shape.
10 . The three-dimensional memory device of claim 1 , wherein the storage stack structure and the selection stack structure comprise dielectric layers and gate layers that are alternately stacked in the second direction.
11 . A three-dimensional (3D) memory device, comprising: a storage stack structure comprising first dielectric layers and first gate layers that are alternately stacked in a second direction; a storage channel structure extending through the storage stack structure in the second direction; a selection stack structure disposed on the storage stack structure and comprising second dielectric layers and second gate layers that are alternately stacked in the second direction; a selection channel structure extending through the selection stack structure in the second direction and contacting the storage channel structure; and a TSG cut structure extending into the selection stack structure in the second direction and extending in a third direction perpendicular to the second direction, wherein the TSG cut structure is a wave shape and located on a side of the selection channel structure in a first direction perpendicular to the second direction and the third direction.
12 . The three-dimensional memory device of claim 11 , wherein the storage channel structure comprises a first end and the selection channel structure comprises a second end in contact with the first end, and a width of the first end is larger than a width of the second end in the first direction.
13 . The three-dimensional memory device of claim 12 , wherein the selection channel structure comprises a third end opposite to the second end in the second direction, and the width of the first end is larger than a width of the third end in the first direction.
14 . The three-dimensional memory device of claim 13 , wherein the width of the second end is smaller than the width of the third end in the first direction.
15 . The three-dimensional memory device of claim 13 , further comprising a selection channel plug comprising a fourth end in contact with the third end and a fifth end opposite to the fourth end, wherein the width of the third end is smaller than a width of the fifth end in the first direction
16 . The three-dimensional memory device of claim 11 , wherein the storage channel structure comprises a channel layer and the selection channel structure comprises a conductive layer, and the channel layer and the conductive layer are both in contact with a storage channel plug.
17 . The three-dimensional memory device of claim 16 , wherein the selection channel structure further comprises a dielectric core surrounded by the conductive layer and an insulating layer between the conductive layer and the selection stack structure.
18 . The three-dimensional memory device of claim 16 , further comprising a selection channel plug in contact with the conductive layer, wherein the conductive layer is between the selection channel plug and the storage channel plug in the second direction, and the conductive layer, the storage channel plug, and the selection channel plug comprise polysilicon.
19 . The three-dimensional memory device of claim 11 , wherein the selection channel structure adjacent to the TSG cut structure is shifted off-axis with respect to the storage channel structure in the first direction away from the TSG cut structure to increase a distance between the TSG cut structure and the selection channel structure.
20 . The three-dimensional memory device of claim 11 , wherein the TSG cut structure comprises a dielectric material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 17/845,308, filed on Jun. 21, 2022, which claims priority to Chinese Patent Application No. 202110687429.2 filed on Jun. 21, 2021, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a three-dimensional memory device and a fabrication method for the same. BACKGROUND Three-dimensional memories (3D NAND) can increase their storage capacities by increasing the number of vertically stacked layers or the storage density of the channel structures. Specifically, the storage density of the three-dimensional memory can be increased by optimizing the arrangement of the channel structures. In some arrangements of the channel structures, the channel structures are divided into multiple rows in a storage block in a mutually staggered arrangement. A top selection gate (TSG) cut structure is formed between the channel structure rows to divide the channel structure rows in a storage block into several parts, to more easily control the divided storage block to perform operations such as programming and erasing. BRIEF SUMMARY The present application provides a fabrication method for a three-dimensional memory. The fabrication method can include forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure. A selection stack structure can be stacked on the storage stack structure and a selection channel structure, which penetrates the selection stack structure, can be connected to the storage channel structure. In some embodiments, a width of the selection channel structure in a first direction, can be smaller than a width of the storage channel structure in the first direction. A TSG cut structure can be formed to penetrate the selection stack structure. In order to avoid overlap between the TSG structure and the channel structure rows, the distance between the channel structure rows can be increased. Alternatively, the TSG cut structure can be formed to penetrate the channel structure row in a middle position, and use the channel structure row in the middle position as a dummy channel structure row. In this alternative arrangement, the channel structures in the channel structure row in the middle position do not have a storage function. Nonetheless, these arrangements limit the ability to increase storage density. Therefore, a need exists to increase storage density in a three-dimensional storage unit while avoiding the overlap between the channel structures and the top select gate structure. In some embodiments, forming the storage stack and the selection channel stack can include alternately disposing dielectric layers and sacrificial layers to form a multi-layered stack. In some embodiments, the method includes forming a selection channel hole that penetrates the selection stack structure and exposes the storage channel structure. The method further includes forming an insulating layer on an inner wall of the selection channel hole followed by removing a part of the insulating layer located at a bottom of the selection channel hole to expose the storage channel structure. Forming a conductive layer on a surface of the insulating layer and the bottom of the selection channel hole. In some embodiments, forming the selection channel structure that penetrates the selection stack structure can further include filling in the selection channel hole where the insulating layer and the conductive layer are formed with a dielectric material. In some embodiments, after filling in the selection channel hole where the insulating layer and the conductive layer are formed with the dielectric material, the method can further include forming a stop layer at an end part of the dielectric material away from the substrate. In some embodiments, forming the stop layer can include removing a part of the dielectric material from the dielectric filled selection channel at an end away from the substrate. This forms a first opening that exposes the conductive layer. The stop layer can be formed in the first recessed hole. The material forming the stop layer can include silicon nitride, for example. In some embodiments, before the step of forming the TSG cut structure that penetrates the selection stack structure, the method can further include forming a cap layer to cover the selection channel structure and a surface of the selection stack structure away from the substrate. In some embodiments, the method can further include removing the sacrificial layers from the alternately stacked dielectric and sacrificial layers in the storage stack structure and the selection stack structure to form sacrificial gaps. The sacrificial gaps can be filled with a conductive material to form a gate layer. In some embodiments, the step of forming the TSG cut struc