US-20260129857-A1 - METHODS FOR FABRICATING A LAYERED SEMICONDUCTOR STRUCTURE FOR NAND MEMORY DEVICES

Abstract

The present disclosure provides a fabrication method to produce a semiconductor structure with increased reliability for use in NAND memory devices. The method can include forming a layered semiconductor structure that includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method can also include forming a channel structure, which can include etching the first layer, the second layer, and the third layer to form an opening through a surface of the semiconductor structure. A portion of the third layer can be exposed at the opening. The forming of the channel structure also include oxidizing the exposed portion of the third layer to form silicon oxide expand the exposed portion of the third layer.

Inventors

• Qian Li
• Shu Wu
• Liang Xiao
• Lei Li
• Hao PU

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A semiconductor structure comprising a first structure comprising: a polysilicon layer; a silicon oxide layer stacked over the polysilicon layer along a first direction; a gate layer stacked over the silicon oxide layer along the first direction; and a channel structure extending through at least the silicon oxide layer and the gate layer along the first direction and in contact with the polysilicon layer, the channel structure comprising: a wide portion having a size defined along a second direction perpendicular to the first direction, wherein the wide portion is disposed intersecting at least the gate layer; and a narrow portion having a size defined along the second direction perpendicular to the first direction, wherein the narrow portion is disposed intersecting at least the polysilicon layer, and the size of the narrow portion is smaller than the size of the wide portion.
2. 2 . The semiconductor structure of claim 1 , wherein the channel structure comprises a first channel structure and a second channel structure extending along the first direction, and a first end of the first channel structure is connected to a second end of the second channel structure.
3. 3 . The semiconductor structure of claim 2 , wherein a size of the first end of the first channel structure in the second direction is greater than a size of the second end of the second channel structure in the second direction.
4. 4 . The semiconductor structure of claim 2 , wherein the first channel structure is in contact with the polysilicon layer and comprises a void.
5. 5 . The semiconductor structure of claim 1 , further comprising a second structure comprising a circuit coupled to the channel structure, wherein the second structure is bonded with the first structure.
6. 6 . The semiconductor structure of claim 5 , wherein the second structure further comprises a pad structure coupled to the first structure, and the pad structure is deposed at a side of the gate layer away from the polysilicon layer along the first direction.
7. 7 . The semiconductor structure of claim 1 , wherein the channel structure comprises at least a semiconductor layer.
8. 8 . The semiconductor structure of claim 7 , wherein the channel structure further comprises a memory layer between the gate layer and the semiconductor layer in the wide portion, and a filling layer surrounded by the semiconductor layer in the wide portion and the narrow portion.
9. 9 . The semiconductor structure of claim 8 , wherein a size of the filling layer along the second direction in the narrow portion is smaller than a size of the filling layer along the second direction in the wide portion.
10. 10 . The semiconductor structure of claim 1 , wherein the channel structure comprises a bottleneck cross-section located between the wide portion and the narrow portion.
11. 11 . A semiconductor structure comprising a first structure comprising: a first semiconductor layer; a stacked layer over the first semiconductor layer in a first direction and comprising interleaved conductive layers and dielectric layers; and a channel structure comprising a second semiconductor layer and extending through the stacked layer and into the first semiconductor layer along the first direction, wherein the channel structure comprises a first portion in contact with the stacked layer and a second portion in contact with the first semiconductor layer, and a first size of the second semiconductor layer in the first portion along a second direction perpendicular to the first direction is greater than a second size of the second semiconductor layer in the second portion along the second direction.
12. 12 . The semiconductor structure of claim 11 , wherein the second semiconductor layer comprises a step structure at an end of the second semiconductor layer close to the first semiconductor layer.
13. 13 . The semiconductor structure of claim 11 , wherein the channel structure comprises a first channel structure extending along the first direction and a second channel structure extending along the first direction, and a first end of the first channel structure is connected to a second end of the second channel structure, wherein a size of the first end of the first channel structure in the second direction is greater than a size of the second end of the second channel structure in the second direction.
14. 14 . The semiconductor structure of claim 13 , wherein the first channel structure is in contact with the first semiconductor layer and comprises a void.
15. 15 . The semiconductor structure of claim 11 , further comprising a second structure comprising a circuit coupled to the channel structure, wherein the second structure is bonded with the first structure.
16. 16 . The semiconductor structure of claim 15 , wherein the second structure further comprises a pad structure coupled to the first structure, and the pad structure is deposed at a side of the stacked layer away from the first semiconductor layer along the first direction.
17. 17 . The semiconductor structure of claim 11 , wherein the channel structure further comprises a memory layer between the stacked layer and the second semiconductor layer in the first portion, and a filling layer surrounded by the second semiconductor layer in the first portion and the second portion.
18. 18 . The semiconductor structure of claim 17 , wherein a size of the filling layer along the second direction in the second portion is smaller than a size of the filling layer along the second direction in the first portion.
19. 19 . The semiconductor structure of claim 17 , wherein the filling layer comprises a step structure at an end of the filling layer close to the first semiconductor layer.
20. 20 . A memory system comprising: a semiconductor structure comprising: a first semiconductor layer; a stacked layer over the first semiconductor layer in a first direction and comprising interleaved conductive layers and dielectric layers; and a channel structure comprising a second semiconductor layer and extending through the stacked layer and into the first semiconductor layer along the first direction, wherein the channel structure comprises a first portion in contact with the stacked layer and a second portion in contact with the first semiconductor layer, and a first size of the second semiconductor layer in the first portion along a second direction perpendicular to the first direction is greater than a second size of the second semiconductor layer in the second portion along the second direction; and a controller coupled to the semiconductor structure.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 17/889,216, filed on Aug. 16, 2022, entitled “METHODS FOR FABRICATING A LAYERED SEMICONDUCTOR STRUCTURE FOR NAND MEMORY DEVICES.” TECHNICAL FIELD The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a method for debugging double program errors in NAND memory. BACKGROUND As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells. In a 3D NAND flash memory, many layers of memory cells can be stacked vertically such that storage density per unit area can be greatly increased. The vertically stacked memory cells can form memory strings, where the channels of the memory cells are connected in each memory string. Each memory cell can be addressed through a word line and a bit line. Data (i.e., logic states) of the memory cells in an entire memory page sharing the same word line can be read or programmed simultaneously. However, due to aggressive scaling, reliability can be a concern for a 3D NAND flash memory. BRIEF SUMMARY Embodiments of methods and systems for data protection in a memory device are described in the present disclosure. In some embodiments, a fabrication method can produce a semiconductor structure with increased reliability for use in NAND memory devices. The method can include forming a semiconductor structure that includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method can also include forming a channel structure, which can include etching the first layer, the second layer, and the polysilicon layer to form an opening through a surface of the semiconductor structure. A portion of the third layer can be exposed at the opening. The forming of the channel structure can also include oxidizing the exposed portion of the third layer to form silicon oxide to expand the exposed portion of the third layer based on the oxidizing. In some embodiments, the oxidizing can include using a wet oxidation process. In some embodiments, the expanding of the exposed portion of the polysilicon layer can narrow a portion of the opening. In some embodiments, the method can also include disposing a first channel layer at the opening. The method can also include disposing a second channel layer within the opening and on the first channel layer. The second channel layer can have the second silicon compound. The method can also include disposing a third channel layer within the opening and on the second channel layer. In some embodiments, the expanding of the exposed portion of the third layer can narrow a portion of the opening. The disposing of the first, second, or third channel layers can obstruct the narrowed portion of the channel. In some embodiments, the method can also include disposing fourth and fifth channel layers within the channel structure. In some embodiments, the method can also include forming a channel end structure. The forming can include disposing a first channel layer at the opening. The forming can also include disposing a second channel layer at the opening and on the first channel layer. The forming can also include disposing a third channel layer at the opening and on the second channel layer. The channel end structure can include a bottleneck cross-section based on the expanded exposed portion of the third layer. In some embodiments, the forming of the semiconductor structure can include forming a layer of silicon oxide for the first layer. In some embodiments, the forming of the semiconductor structure can include forming a layer of silicon nitride for the second layer. In some embodiments, the oxidizing can include performing a wet oxidation process using gasses having a temperature greater than approximately 600 degrees Celsius and less than approximately 800 degrees Celsius. In some embodiments, the oxidizing can include exposing the exposed portion of the polysilicon layer to hydrogen gas and oxygen gas. In some embodiments, a ratio of the hydrogen gas to the oxygen gas can be greater than approximately 0.14 and less than approximately 7.00. In some embodiments, the oxidizing can also include performing the exposing of the exposed portion of the polysilicon layer to the hydrogen and oxygen gasses for a duration greater than approximately 0.5 hours and less than approximately 12.0 hours. In some embodiments, the oxidizing can include exposing the exposed portion of the third layer to nitrogen gas. In some embodiments, the semiconductor structure can include a sacrificial layer affixed to at least the first layer. The etching can also include etching the sacrificial layer. In some embod