US-20260129858-A1 - THREE-DIMENSIONAL MEMORY, THE MANUFACTURING METHOD FOR THE SAME, AND MEMORY SYSTEM

Abstract

A three-dimensional memory includes a bottom select gate structure, a stack structure disposed on the bottom select gate structure, and a top select gate structure disposed on the stack structure. The stack structure includes a channel layer extending in stack structure in the first direction of the thickness of the stack structure. The channel layer has a first conductive type impurity. At least one of the bottom select gate structure or the top select gate structure includes a semiconductor structure extending in the first direction and connected with the channel layer and having a second conductive type impurity different from the first conductive type impurity.

Inventors

• Xiaoxin LIU
• Lei Xue

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20251229

Claims (20)

1. 1 . A three-dimensional memory, comprising: a stack structure comprising a channel layer extending in a first direction and a channel plug located above the channel layer; and a top select gate structure disposed on the stack structure and comprising a stack layer, a semiconductor structure, and a conductive plug located above the semiconductor structure, wherein the semiconductor structure extends through the stack layer in the first direction and connects to the channel plug, the channel plug comprises an N-type impurity, and the conductive plug comprises a same type of impurity as the channel plug.
2. 2 . The three-dimensional memory of claim 1 , wherein the semiconductor structure is a semiconductor fill layer disposed in the top select gate structure; and the top select gate structure comprises: the semiconductor fill layer extending in the first direction, and the conductive plug located above the semiconductor fill layer and connected to the semiconductor fill layer; and a barrier layer disposed on a sidewall of the semiconductor fill layer.
3. 3 . The three-dimensional memory of claim 1 , wherein the semiconductor structure is a semiconductor thin film layer disposed in the top select gate structure; the top select gate structure comprises: an insulating dielectric fill layer extending in the first direction; and the semiconductor thin film layer and a barrier layer, in sequence, disposed on a sidewall of the insulating dielectric fill layer, the conductive plug being located above the semiconductor thin film layer and the insulating dielectric fill layer and connected to the semiconductor thin film layer.
4. 4 . The three-dimensional memory of claim 2 , wherein the barrier layer surrounds sidewalls of the conductive plug and the semiconductor structure.
5. 5 . The three-dimensional memory of claim 1 , wherein the channel layer connects to the semiconductor structure through the channel plug.
6. 6 . The three-dimensional memory of claim 1 , wherein both the conductive plug and the channel plug comprise the N-type impurity.
7. 7 . The three-dimensional memory of claim 6 , wherein impurity doping concentrations of both the conductive plug and the channel plug are greater than an impurity doping concentration of the semiconductor structure.
8. 8 . The three-dimensional memory of claim 1 , wherein the stack layer comprises a top select gate layer and a top dielectric layer.
9. 9 . The three-dimensional memory of claim 8 , wherein the top select gate layer is a semiconductor gate layer.
10. 10 . The three-dimensional memory of claim 9 , wherein the semiconductor gate layer has an impurity doping concentration of 10 19 cm -3 to 10 21 cm -3 .
11. 11 . The three-dimensional memory of claim 8 , wherein the top select gate layer is a metal gate layer.
12. 12 . The three-dimensional memory of claim 1 , wherein the semiconductor structure has an impurity doping concentration of 10 13 cm -3 to 10 15 cm -3 ; and the conductive plug and the channel plug have impurity doping concentrations of 10 19 cm -3 to 10 21 cm -3 .
13. 13 . A three-dimensional memory, comprising: a stack structure comprising a channel layer extending in a first direction and a channel plug located above the channel layer; and a top select gate structure disposed on the stack structure and comprising a stack layer, a semiconductor structure, and a conductive plug located above the semiconductor structure, wherein the semiconductor structure extends through the stack layer in the first direction and connects to the channel plug, the channel plug comprises an N-type impurity, and impurity doping concentrations of both the conductive plug and the channel plug are greater than an impurity doping concentration of the semiconductor structure.
14. 14 . The three-dimensional memory of claim 13 , wherein the semiconductor structure is a semiconductor fill layer disposed in the top select gate structure; and the top select gate structure comprises: the semiconductor fill layer extending in the first direction, and the conductive plug located above the semiconductor fill layer and connected to the semiconductor fill layer; and a barrier layer disposed on a sidewall of the semiconductor fill layer.
15. 15 . The three-dimensional memory of claim 13 , wherein the semiconductor structure is a semiconductor thin film layer disposed in the top select gate structure; the top select gate structure comprises: an insulating dielectric fill layer extending in the first direction; and the semiconductor thin film layer and a barrier layer, in sequence, disposed on a sidewall of the insulating dielectric fill layer, the conductive plug being located above the semiconductor thin film layer and the insulating dielectric fill layer and connected to the semiconductor thin film layer.
16. 16 . The three-dimensional memory of claim 14 , wherein the barrier layer surrounds sidewalls of the conductive plug and the semiconductor structure.
17. 17 . The three-dimensional memory of claim 13 , wherein both the conductive plug and the channel plug comprise the N-type impurity.
18. 18 . The three-dimensional memory of claim 13 , wherein the stack layer comprises a top select gate layer and a top dielectric layer, the top select gate layer is a semiconductor gate layer, and the semiconductor gate layer has an impurity doping concentration of 10 19 cm -3 to 10 21 cm -3 .
19. 19 . The three-dimensional memory of claim 13 , wherein the stack layer comprises a top select gate layer and a top dielectric layer, and the top select gate layer is a metal gate layer.
20. 20 . The three-dimensional memory of claim 13 , wherein the semiconductor structure has an impurity doping concentration of 10 13 cm -3 to 10 15 cm -3 ; and the conductive plug and the channel plug have impurity doping concentrations of 10 19 cm -3 to 10 21 cm -3 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. Application No. 18/090,981, filed on December 29, 2022, which is a continuation of International Application No. PCT/CN2021/140044, filed on December 21, 2021, both of which are incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure relates to the field of semiconductor design and manufacturing, and more particularly to a three-dimensional (3D) memory, a manufacturing method of a 3D memory, and a memory system. BACKGROUND A select gate structure, such as at least one of a bottom select gate structure and a top select gate structure, is generally provided in a three-dimensional memory to enable the turn-off and turn-on operations of the three-dimensional memory during data operation. However, with the increase in the number of stacked layers in the 3D memory and the thin dielectric film layers included in the 3D memory becoming more and more complex, 3D memory’s turn-off and turn-on performance is adversely affected. SUMMARY The present disclosure provides a three-dimensional memory and a manufacturing method capable of at least partially solving the above problems existing in the related art. An aspect of the present disclosure provides a three-dimensional memory that comprises: a bottom select gate structure; a stack structure disposed on the bottom select gate structure, and comprising a channel layer extending in the stack structure in a first direction, the channel layer having a first conductive type impurity, the first direction being a direction of a thickness of the stack structure; and a top select gate structure disposed on the stack structure, wherein at least one of the bottom select gate structure and the top select gate structure comprises a semiconductor structure extending in the first direction and connected with the channel layer, wherein the semiconductor structure has a second conductive type impurity opposite to the first conductive type impurity. In an implementation, the semiconductor structure is a first semiconductor fill layer disposed in the bottom select gate structure, wherein the bottom select gate structure comprises: a first vertically-extending hole extending in the first direction; a first barrier layer disposed on inner walls of the first vertically-extending hole; and the first semiconductor fill layer filled in a remaining space of the first vertically-extending hole. In an implementation, the semiconductor structure is a first semiconductor thin film layer disposed in the bottom select gate structure, wherein the bottom select gate structure comprises: a first vertically-extending hole extending in the first direction; a first barrier layer, and the first semiconductor thin film layer disposed on inner walls of the first vertically-extending hole in sequence; and a first insulating dielectric fill layer filled in a remaining space of the first vertically-extending hole. In an implementation, the semiconductor structure is a semiconductor fill layer or a first semiconductor thin film layer, the memory further comprising: a semiconductor connect layer located below and connected with the first semiconductor fill layer or the first semiconductor thin film layer, wherein the semiconductor connect layer has the first conductive type impurity. In an implementation, an impurity doping concentration of the semiconductor connect layer is greater than an impurity doping concentration of the first semiconductor fill layer or the first semiconductor thin film layer. In an implementation, the semiconductor structure is a second semiconductor fill layer disposed in the top select gate structure, wherein the top select gate structure comprises: a second vertically-extending hole extending in the first direction; a second barrier layer disposed on inner walls of the second vertically-extending hole; and the second semiconductor fill layer and a conductive plug filled in a remaining space of the second vertically-extending hole, wherein the conductive plug is located above the second semiconductor fill layer and is connected with the second semiconductor fill layer. In an implementation, the semiconductor structure is a second semiconductor thin film layer disposed in the top select gate structure, wherein the top select gate structure comprises: a second vertically-extending hole extending in the first direction; a second barrier layer disposed on inner walls of the second vertically-extending hole; the second semiconductor thin film layer and a conductive plug disposed on a surface of the second barrier layer; and a second insulating dielectric fill layer disposed on a surface of the second semiconductor thin film layer, wherein the conductive plug is located above the second semiconductor thin film layer and the second insulating dielectric fill layer, and the conductive plug is connected with the second semiconductor thin film layer. In an implementation, the semi