US-20260129859-A1 - IC MEMORY DEVICE IMPLEMENTING AN IMPLY FUNCTION

Abstract

Some embodiments relate to an integrated circuit. The integrated circuit includes an inter-level dielectric (ILD) structure disposed over a substrate and surrounding a plurality of conductive interconnects. A first memory device is arranged within the ILD structure and includes a first data storage structure and a first channel structure arranged vertically between a first conductive structure and a second conductive structure. A second memory device is arranged within the ILD structure and includes a second data storage structure and a second channel structure arranged vertically between a third conductive structure and a fourth conductive structure. A fifth conductive structure is arranged within the ILD structure and contacts the first channel structure and the second channel structure.

Inventors

• Yun-Feng KAO
• Katherine H. Chiang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20251230

Claims (20)

1. 1 . An integrated circuit, comprising: an inter-level dielectric (ILD) structure disposed over a substrate and surrounding a plurality of conductive interconnects; a first memory device arranged within the ILD structure and comprising a first data storage structure and a first channel structure arranged vertically between a first conductive structure and a second conductive structure; a second memory device arranged within the ILD structure and comprising a second data storage structure and a second channel structure arranged vertically between a third conductive structure and a fourth conductive structure; and a fifth conductive structure arranged within the ILD structure and contacting the first channel structure and the second channel structure.
2. 2 . The integrated circuit of claim 1 , wherein the fifth conductive structure has opposing outermost sidewalls that are laterally confined between outer edges of the first memory device and the second memory device.
3. 3 . The integrated circuit of claim 1 , wherein the fifth conductive structure is laterally separated from sidewalls of the second conductive structure and the fourth conductive structure by the ILD structure, wherein the sidewalls of the second conductive structure and the fourth conductive structure face the fifth conductive structure.
4. 4 . The integrated circuit of claim 1 , wherein the fifth conductive structure is at a substantially same height over the substrate as both the second conductive structure and the fourth conductive structure.
5. 5 . The integrated circuit of claim 1 , wherein the first data storage structure continuously and laterally extends past outermost sidewalls of the second conductive structure and the fifth conductive structure that face one another.
6. 6 . The integrated circuit of claim 1 , wherein the ILD structure comprises a lower surface over the fifth conductive structure and a protrusion that extends outward from the lower surface to laterally between the second conductive structure and the fifth conductive structure.
7. 7 . The integrated circuit of claim 6 , wherein the protrusion vertically contacts an upper surface of the first channel structure.
8. 8 . The integrated circuit of claim 1 , wherein the first memory device and the second memory device comprise ferroelectric memory devices.
9. 9 . An integrated circuit, comprising: a first ferroelectric device comprising a first ferroelectric structure arranged vertically between a substrate and a first gate structure and laterally between a first source-drain region and a second source-drain region in a cross-sectional view; a second ferroelectric device coupled in series with the first ferroelectric device, the second ferroelectric device comprising a second ferroelectric structure arranged vertically between the substrate and a second gate structure and laterally between the second source-drain region and a third source-drain region in the cross-sectional view; and wherein the second source-drain region continuously extends between the first ferroelectric device and the second ferroelectric device.
10. 10 . The integrated circuit of claim 9 , wherein the second source-drain region continuously extends from directly below the first ferroelectric device to directly below the second ferroelectric device.
11. 11 . The integrated circuit of claim 9 , further comprising: a first conductive contact arranged on the first source-drain region; a second conductive contact arranged on the third source-drain region; and wherein a conductive contact is not arranged on the second source-drain region in the cross-sectional view.
12. 12 . The integrated circuit of claim 9 , wherein the first ferroelectric device comprises one or more first sidewall spacers arranged along opposing sides of the first gate structure; and wherein the second ferroelectric device comprises one or more second sidewall spacers arranged along opposing sides of the second gate structure.
13. 13 . The integrated circuit of claim 12 , further comprising: a dielectric arranged over the substrate and laterally surrounding the first gate structure and the second gate structure; a first conductive contact extending through the dielectric to contact the first source-drain region; a second conductive contact extending through the dielectric to contact the third source-drain region; and wherein the dielectric has a lower surface that is over the second source-drain region and that continuously extends between the one or more first sidewall spacers and the one or more second sidewall spacers.
14. 14 . An integrated circuit, comprising: an inter-level dielectric (ILD) arranged over a substrate; a first memory device arranged within the ILD and comprising a first data storage structure and a first channel laterally extending between a first source-drain and a second source-drain; a second memory device arranged within the ILD and comprising a second data storage structure and a second channel laterally extending between the second source-drain and a third source-drain; a first conductive contact arranged on the first source-drain; a second conductive contact arranged on the third source-drain; and wherein the ILD continuously extends between the first conductive contact and the second conductive contact in a cross-sectional view.
15. 15 . The integrated circuit of claim 14 , wherein the ILD comprises a lower part that is laterally between sides of the first memory device and the second memory device and that is vertically below the second source-drain; and wherein the ILD comprises an upper part that is over the second source-drain.
16. 16 . The integrated circuit of claim 14 , wherein the second source-drain is a conductor arranged laterally between the first source-drain and the third source-drain and contacting upper surfaces of the first channel and the second channel.
17. 17 . The integrated circuit of claim 14 , wherein the second source-drain has a greater width than the first source-drain or the third source-drain.
18. 18 . The integrated circuit of claim 14 , wherein the first memory device comprises a charge-trapping memory device, a flash memory device, or a ferroelectric memory device.
19. 19 . The integrated circuit of claim 14 , wherein the ILD completely covers a topmost surface of the second source-drain.
20. 20 . The integrated circuit of claim 14 , wherein the first source-drain and the third source-drain are asymmetric about the first data storage structure.

Description

REFERENCE TO RELATED APPLICATION This Application is a Continuation of U.S. Application Ser. No. 18/346,981, filed on Jul. 5, 2023, the contents of which are hereby incorporated by reference in their entirety. BACKGROUND Many modern-day electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to retain its stored data in the absence of power, whereas volatile memory loses its stored data when power is lost. Some efforts have been made to incorporate standard logic functionality within electronic memory (e.g., non-volatile memory) by way of in-memory computing to perform some preliminary data processing on stored data without explicitly reading the stored data from the memory into a central processing unit (CPU) beforehand. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A illustrates a schematic view of some embodiments of a portion of an integrated circuit (IC) memory device including two charge-trapping devices to implement an IMPLY function, according to the present disclosure. FIG. 1B illustrates a voltage graph describing the operation of the charge-trapping devices in some embodiments of the portion of the IC memory device of FIG. 1A, according to the present disclosure. FIGS. 2A through 2D illustrate a more detailed example of a series of operations using the IC memory device of FIG. 1A to implement an IMPLY function. FIG. 2E illustrates a cross-sectional view of some embodiments of the portion of the IC memory device of FIG. 1A resulting from front end of line (FEOL) processing. FIG. 2F illustrates a cross-sectional view of some embodiments of the portion of the IC memory device of FIG. 1A resulting from back end of line (BEOL) processing. FIGS. 3A through 3G illustrate a series of operations using an IC memory device that includes three charge-trapping devices to implement a NAND function using a series of IMPLY functions. FIG. 3H illustrates a cross-sectional view of some embodiments of the portion of an IC memory device of FIG. 3A resulting from FEOL processing. FIG. 3I illustrates a cross-sectional view of some embodiments of the portion of the IC memory device of FIG. 3A resulting from BEOL processing. FIG. 4 illustrates a methodology in flowchart format that illustrates some embodiments of operation of the IC memory device of FIGS. 2A-2F. FIG. 5 illustrates a methodology in flowchart format that illustrates some embodiments of operation of the IC memory device of FIGS. 3A-3I. FIG. 6 illustrates a schematic view of some embodiments of a portion of an IC memory device including five charge-trapping devices to implement a logic function using one or more IMPLY functions, according to the present disclosure. FIGS. 7A through 7F illustrate some embodiments of a series of incremental manufacturing steps as a series of cross-sectional views of the IC memory device of FIG. 6 resulting from FEOL processing. FIG. 8 illustrates a methodology in flowchart format that illustrates some embodiments of the present concept related to FIGS. 7A through 7E. FIGS. 9A through 9F illustrate some embodiments of a series of incremental manufacturing steps as a series of cross-sectional views of the IC memory device of FIG. 6 resulting from BEOL processing. FIG. 10 illustrates a methodology in flowchart format that illustrates some embodiments of the present concept related to FIGS. 9A through 9F. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or