US-20260129860-A1 - SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Abstract

A semiconductor device may include an element isolation film on a substrate, a first gate electrode, and an auxiliary electrode on the element isolation film. The element isolation film may define a first active area of the substrate. A first source/drain area and a second source/drain area of a first conductivity type may be in the first active area. The second source/drain area may be spaced apart from the first source/drain area in a first direction. The first gate electrode may be on a portion of the first active area between the first source/drain area and the second source/drain area. The first gate electrode may extend in a second direction crossing the first direction. The substrate may include an impurity area surrounding the element isolation film. The impurity area may contain a second conductivity type impurity. The auxiliary electrode and the impurity area may be electrically connected to each other.

Inventors

• Dong Kyu Kim
• Jun Seok OH
• Sea Hoon Lee
• Seong Pil CHANG

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250609

Priority Date

20241104

Claims (20)

1. 1 . A semiconductor device comprising: a substrate; an element isolation film on the substrate, the element isolation film defining a first active area of the substrate, the first active area of the substrate including a first source/drain area and a second source/drain area in the first active area, the first source/drain area contacting the element isolation film in a first direction and having a first conductivity type, the second source/drain area being spaced apart from the first source/drain area in the first direction and having the first conductivity type; a first gate electrode on a portion of the first active area between the first source/drain area and the second source/drain area, wherein the first gate electrode extends in a second direction and the second direction intersects the first direction; a second gate electrode on the first active area and extending in the second direction, wherein the second source/drain area is between the first gate electrode and the second gate electrode; and a first auxiliary electrode on the element isolation film, wherein in a plan view, the first auxiliary electrode does not overlap the first source/drain area in the second direction and the first auxiliary electrode overlaps the second source/drain area in the second direction.
2. 2 . The semiconductor device of claim 1 , wherein a ground voltage is applied to the first auxiliary electrode.
3. 3 . The semiconductor device of claim 1 , wherein the substrate further includes an impurity area in the substrate and the impurity area surrounds the element isolation film, the impurity area contains an impurity having a second conductivity type, and the second conductivity type is different from the first conductivity type.
4. 4 . The semiconductor device of claim 3 , wherein in the plan view, the first auxiliary electrode is between the second source/drain area and the impurity area.
5. 5 . The semiconductor device of claim 3 , further comprising: a connection pattern connecting the first auxiliary electrode and the impurity area to each other, wherein a ground voltage is applied to the impurity area.
6. 6 . The semiconductor device of claim 3 , wherein the first conductivity type is an n-type, and the second conductivity type is a p-type.
7. 7 . The semiconductor device of claim 1 , wherein the first gate electrode and the first auxiliary electrode do not overlap each other in the first direction.
8. 8 . The semiconductor device of claim 1 , wherein the first gate electrode and the first auxiliary electrode do not overlap each other in the second direction.
9. 9 . The semiconductor device of claim 1 , wherein the first gate electrode and the first auxiliary electrode are at a same level.
10. 10 . The semiconductor device of claim 1 , wherein the first active area of the substrate further includes a third source/drain area in the first active area, the third source/drain area is in contact with the element isolation film in the first direction and the third source/drain area has the first conductivity type, the second gate electrode is on a portion of the first active area between the second source/drain area and the third source/drain area, and in the plan view, the first auxiliary electrode does not overlap with the third source/drain area in the second direction.
11. 11 . The semiconductor device of claim 1 , further comprising: a third gate electrode; and a second auxiliary electrode on the element isolation film, wherein the first active area of the substrate further includes a third source/drain area and a fourth source/drain area in the first active area, the third source/drain area is spaced from the second source/drain area in the first direction, and the third source/drain area has the first conductivity type, the fourth source/drain area is spaced from the third source/drain area in the first direction, the fourth source/drain area contacts the element isolation film in the first direction, and the fourth source/drain area has the first conductivity type, the third gate electrode is on a portion of the first active area between the third source/drain area and the fourth source/drain area, the third gate electrode extends in the second direction, and in the plan view, the second auxiliary electrode overlaps the third source/drain area in the second direction and does not overlap the fourth source/drain area in the second direction.
12. 12 . The semiconductor device of claim 11 , wherein the second auxiliary electrode is spaced apart from the first auxiliary electrode in the first direction.
13. 13 . The semiconductor device of claim 11 , wherein the first auxiliary electrode and the second auxiliary electrode are at a same level.
14. 14 . The semiconductor device of claim 1 , further comprising: a cell substrate, the cell substrate being spaced apart from the substrate in a vertical direction, the vertical direction intersecting an upper surface of the substrate; a plurality of word-lines sequentially stacked on the cell substrate; a channel structure on the cell substrate, the channel structure intersecting the plurality of word-lines; and a bit-line contacting the channel structure, wherein the first source/drain area is electrically connected to one of the plurality of word-lines.
15. 15 . A semiconductor device comprising: a substrate; an element isolation film on the substrate, the element isolation film defining a first active area of the substrate, the first active area of the substrate including a first source/drain area and a second source/drain area in the first active area, the first source/drain area having a first conductivity type, the second source/drain area being spaced apart from the first source/drain area in a first direction and having the first conductivity type; a first gate electrode on a portion of the first active area between the first source/drain area and the second source/drain area, wherein the first gate electrode extends in a second direction and the second direction intersects the first direction; an auxiliary electrode on the element isolation film, wherein the substrate includes an impurity area surrounding the element isolation film, the impurity area contains an impurity having a second conductivity type, the second conductivity type is different from the first conductivity type, and the auxiliary electrode and the impurity area are electrically connected to each other.
16. 16 . The semiconductor device of claim 15 , wherein a ground voltage is applied to the auxiliary electrode and the impurity area.
17. 17 . The semiconductor device of claim 15 , further comprising: a second gate electrode, wherein the first active area further includes a third source/drain area in the first active area, the third source/drain area is in contact with the element isolation film in the first direction, and the third source/drain area has the first conductivity type, the second gate electrode is on a portion of the first active area between the second source/drain area and the third source/drain area, the second gate electrode extends in the second direction, in a plan view, the auxiliary electrode does not overlap with the third source/drain area in the second direction.
18. 18 . The semiconductor device of claim 17 , wherein in the plan view, the auxiliary electrode is between the second source/drain area and the impurity area.
19. 19 . The semiconductor device of claim 15 , further comprising: a cell substrate spaced apart from the substrate in a vertical direction, the vertical direction intersecting an upper surface of the substrate; a plurality of word-lines sequentially stacked on the cell substrate; a channel structure on the cell substrate and intersecting the plurality of word-lines; and a bit-line contacting the channel structure, wherein the first source/drain area is electrically connected to one of the plurality of word-lines.
20. 20 . An electronic system comprising: a main substrate; a semiconductor device on the main substrate, the semiconductor device including a first substrate having a peripheral circuit area and a second substrate having a cell area; and a main controller on the main substrate and electrically connected to the semiconductor device, wherein the semiconductor device comprises an element isolation film on the first substrate, a first gate electrode, a second gate electrode, an auxiliary electrode on the element isolation film, a plurality of word-lines sequentially stacked on the second substrate, and a channel structure on the second substrate and intersecting the plurality of word-lines, and a bit-line contacting the channel structure, the element isolation film defines a first active area in the first substrate, the first active area includes a first source/drain area and a second source/drain area, the first source/drain area contacts the element isolation film in a first direction and has a first conductivity type, the second source/drain area is spaced apart from the first source/drain area in the first direction and has the first conductivity type, the first gate electrode is on a portion of the first active area between the first source/drain area and the second source/drain area, the first gate electrode extends in a second direction, the second direction intersects the first direction, the second gate electrode is on the first active area and extends in the second direction, the second source/drain area is between the first gate electrode and the second gate electrode, and in a plan view, the auxiliary electrode does not overlap the first source/drain area in the second direction and the auxiliary electrode overlaps the second source/drain area in the second direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority from Korean Patent Application No. 10-2024-0154177 filed on Nov. 4, 2024 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference. BACKGROUND Field The present disclosure relates to a semiconductor device and/or an electronic system including the same. More specifically, the present disclosure relates to a semiconductor device including memory cells arranged three-dimensionally and/or an electronic system including the same. Description of Related Art As an electronic product becomes lighter, thinner, and simpler, the demand for high integration of a semiconductor device is increasing. As the semiconductor device becomes more highly integrated, sizes of components in the semiconductor device (for example, a transistor) may further decrease, thereby causing leakage current. Therefore, there is a need to control the leakage current of the semiconductor device to improve performance and/or reliability of the semiconductor device. In an electronic system that requires data storage, a semiconductor device that may store high-capacity data therein may be required. Accordingly, a scheme to increase the data storage capacity of the semiconductor device is being studied. For example, in one approach to increase the data storage capacity of the semiconductor device, a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. SUMMARY The present disclosure relates to a semiconductor device with improved performance and reliability. The present disclosure relates to an electronic system including a semiconductor device with improved performance and reliability. Aspects of the present disclosure are not limited to the aspects mentioned above, and other aspects not mentioned may be clearly understood by those skilled in the art from descriptions as set forth below. According to an embodiment of the present disclosure, a semiconductor device may include a substrate; an element isolation film on the substrate, the element isolation film defining a first active area of the substrate, the first active area of the substrate including a first source/drain area and a second source/drain area in the first active area, the first source/drain area contacting the element isolation film in a first direction and having a first conductivity type, the second source/drain area being spaced apart from the first source/drain area in the first direction and having the first conductivity type; a first gate electrode on a portion of the first active area between the first source/drain area and the second source/drain area, wherein the first gate electrode extends in a second direction and the second direction intersects the first direction; a second gate electrode on the first active area and extending in the second direction, wherein the second source/drain area is between the first gate electrode and the second gate electrode; and a first auxiliary electrode disposed on the element isolation film. In a plan view, the first auxiliary electrode may not overlap the first source/drain area in the second direction and the first auxiliary electrode may overlap the second source/drain area in the second direction. According to an embodiment of the present disclosure, a semiconductor device may include a substrate; an element isolation film on the substrate, the element isolation film defining a first active area of the substrate, the first active area of the substrate including a first source/drain area and a second source/drain area in the first active area, the first source/drain area having a first conductivity type, the second source/drain area being spaced apart from the first source/drain area in a first direction and having the first conductivity type; a first gate electrode on a portion of the first active area between the first source/drain area and the second source/drain area, wherein the first gate electrode extends in a second direction and the second direction intersects the first direction; an auxiliary electrode on the element isolation film. The substrate may include an impurity area surrounding the element isolation film. The impurity area may contain an impurity having a second conductivity type. The second conductivity type may be different from the first conductivity type, and the auxiliary electrode and the impurity area may be electrically connected to each other. According to an embodiment of the present disclosure, an electronic system may include a main substrate; a semiconductor device on the main substrate, the semiconductor device including a first substrate having a peripheral circuit area and a second substrate having a cell area; and a main controller on the main substrate and electrically connected to the semiconductor device. The semicond