US-20260129862-A1 - SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Abstract

A semiconductor memory device includes a back gate electrode, a gate electrode on the back gate electrode, a channel layer between the gate electrode and the back gate electrode, a gate insulating layer between the channel layer and the gate electrode, and a ferroelectric layer between the back gate electrode and the channel layer.

Inventors

• Yukio Hayakawa
• Bongyong Lee
• HYUNMOG PARK
• SIYEON CHO

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251231

Priority Date

20220401

Claims (10)

1. 1 . A method of operating a semiconductor memory device, the semiconductor memory device including a plurality of cell strings connected between a bit line and a common source line, wherein each cell string of the plurality of cell strings includes a back gate electrode, a plurality of gate electrodes on the back gate electrode, a channel layer between the plurality of gate electrodes and the back gate electrode, a ferroelectric layer between the back gate electrode and the channel layer, and a gate insulating layer between the channel layer and the plurality of gate electrodes, the method comprising: applying a first program voltage to the back gate electrode of a selected cell string of the plurality of cell strings; and applying a second program voltage to a selected gate electrode of the selected cell string.
2. 2 . The method of claim 1 , wherein the second program voltage is greater than the first program voltage, and the second program voltage is greater than a minimum voltage for changing a polarization of a dipole in the ferroelectric layer.
3. 3 . The method of claim 1 , further comprising applying a pass voltage to unselected gate electrodes in the selected cell string, wherein the pass voltage induces an inversion region in the channel layer.
4. 4 . The method of claim 1 , further comprising applying a third program voltage to back gate lines of unselected cell strings the plurality of cell strings.
5. 5 . The method of claim 4 , wherein the third program voltage is greater than the first program voltage and less than the second program voltage.
6. 6 . The method of claim 5 , wherein a voltage difference between a ground voltage and the third program voltage is smaller than a minimum voltage for changing a polarization of a dipole in the ferroelectric layer.
7. 7 . A method of operating a semiconductor memory device, the semiconductor memory device including a plurality of bit lines, a common source line, and a plurality of cell strings connected between each of the bit lines and the common source line, wherein each cell string of the plurality of cell strings includes a back gate electrode, a plurality of gate electrodes on the back gate electrode, a channel layer between the plurality of gate electrodes and the back gate electrode, a ferroelectric layer between the back gate electrode and the channel layer, and a gate insulating layer between the channel layer and the plurality of gate electrodes, the method comprising: applying a bit line voltage to a selected bit line of the plurality of bit lines; applying a ground voltage to an unselected bit line of the plurality of bit lines, applying a read voltage to a selected gate electrode of selected cell string of the plurality of cell strings; applying a pass voltage to unselected gate electrodes of the plurality of gate electrodes; and applying a ground voltage to back gate electrodes of the plurality of cell strings.
8. 8 . The method of claim 7 , wherein the read voltage is smaller than the pass voltage.
9. 9 . A method of operating a semiconductor memory device, the semiconductor memory device including a plurality of bit lines, a common source line, and a plurality of cell strings connected between each of the bit lines and the common source line, wherein each cell string of the plurality of cell strings includes a back gate electrode, a plurality of gate electrodes on the back gate electrode, a channel layer between the plurality of gate electrodes and the back gate electrode, a ferroelectric layer between the back gate electrode and the channel layer, and a gate insulating layer between the channel layer and the plurality of gate electrodes, the method comprising: applying a ground voltage to the plurality of bit lines of the plurality of cell strings in each memory block; applying a pass voltage to the gate electrodes of the plurality of cell strings; and applying an erase voltage to the back gate electrodes of the plurality of cell strings.
10. 10 . The method of claim 9 , wherein the erase voltage is greater than the pass voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of and claims the benefit of priority to U.S. patent application Ser. No. 18/153,630, filed Jan. 12, 2023, which is a U.S. non-provisional patent application that claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0041184, filed on Apr. 1, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND The inventive concepts relate to semiconductor memory devices and electronic systems including the same. A semiconductor device capable of storing high-capacity data in an electronic system for data storage is required. Accordingly, a method for increasing the data storage capacity of a semiconductor device is studied. For example, as a method for increasing the data storage capacity of the semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed. SUMMARY Some example embodiments of the inventive concepts provide a low-power and high-speed semiconductor memory device. Some example embodiments of the inventive concepts provide an electronic system including a semiconductor memory device. The inventive concepts are not limited to the above-described example embodiments, and some example embodiments, which are not described above, may be clearly understood by those skilled in the art through the following specification. According to some example embodiments of the inventive concepts, a semiconductor memory device may include a back gate electrode, a gate electrode on the back gate electrode, a channel layer between the gate electrode and the back gate electrode, a gate insulating layer between the channel layer and the gate electrode, and a ferroelectric layer between the back gate electrode and the channel layer. According to some example embodiments of the inventive concepts, a semiconductor memory device may include a plurality of cell strings connected between a bit line and a common source line, each cell string of the plurality of cell strings may include a plurality of cell transistors connected in series, and each cell transistor of the plurality of cell transistors may include a back gate electrode, a gate electrode surrounding the back gate electrode, a channel layer between the gate electrode and the back gate electrode, a ferroelectric layer between the channel layer and the back gate electrode, and a gate insulating layer between the gate electrode and the channel layer. According to some example embodiments of the inventive concepts, a semiconductor memory device may include a stacked structure including gate electrodes and interlayer insulating layers vertically alternately stacked on a substrate, and vertical structures passing through the stacked structure, and each vertical structure of the vertical structures may include a back gate electrode extending in a first direction perpendicular to a top surface of the substrate, a ferroelectric layer surrounding the back gate electrode, and a channel layer surrounding the ferroelectric layer. According to some example embodiments of the inventive concepts, an electronic system may include a semiconductor memory device including a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate and peripheral circuit wirings connected to the peripheral circuits; a plurality of cell strings connected between a bit line and a common source line, wherein each cell string of the plurality of cell strings may include a cell array structure including a back gate electrode, a plurality of gate electrodes on the back gate electrode, a channel layer between the plurality of gate electrodes and the back gate electrode, a ferroelectric layer between the back gate electrode and the channel layer, and a gate insulating layer between the channel layer and the plurality of gate electrodes; and an input/output pad electrically connected to the peripheral circuits, and a controller electrically connected to the semiconductor memory device through the input/output pad, the controller configured to control the semiconductor memory device. According to some example embodiments of the inventive concepts, a method of operating a semiconductor memory device that includes a plurality of cell strings connected between a bit line and a common source line, wherein each cell string of the plurality of cell strings includes a back gate electrode, a plurality of gate electrodes on the back gate electrode, a channel layer between the plurality of gate electrodes and the back gate electrode, a ferroelectric layer between the back gate electrode and the channel layer, and a gate insulating layer between the channel layer and the plurality of gate electrodes, may include applying a first program voltage to the back gate electrode of a selected cell string and applying a second progr