US-20260129863-A1 - SEMICONDUCTOR DEVICES

US20260129863A1US 20260129863 A1US20260129863 A1US 20260129863A1US-20260129863-A1

Abstract

A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate and extending in a second direction, and a plurality of channel layers on the active region. The plurality of channel layers are spaced apart from each other in a third direction perpendicular to an upper surface of the substrate. The device includes a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers include at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers has a different coercive voltage. The device includes source/drain regions in recess regions in which the active region is recessed, the source/drain regions are on both sides of the gate electrode, and the source/drain regions are in contact with the plurality of channel layers.

Inventors

Daewon HA
Kyunghwan Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20220228

Claims (20)

1 . A semiconductor device comprising: a memory cell array including a plurality of memory elements; and a peripheral circuit region including peripheral circuits configured to control the memory cell array, wherein each of the plurality of memory elements includes an active region extending in a first direction, a gate electrode intersecting the active region, the gate electrode extending in a second direction, a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the active region, and the plurality of channel layers surrounded by the gate electrode, and a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and wherein in each of the plurality of memory elements, a number of the plurality of channel layers is N, where N is a natural number equal to or greater than 2 , and each of the plurality of memory elements is configured to store N bits of data or less.
2 . The semiconductor device of claim 1 , wherein the peripheral circuit region is configured to sequentially apply a first program voltage and a second program voltage to the gate electrode of a selected memory element in a program operation of writing first data to a selected one of the plurality of memory elements, and the first program voltage has a different sign than the second program voltage.
3 . The semiconductor device of claim 2 , wherein the first program voltage has a different magnitude than the second program voltage.
4 . The semiconductor device of claim 2 , wherein a magnitude of the first program voltage is greater than a magnitude of the second program voltage.
5 . The semiconductor device of claim 2 , wherein in the first data, at least portions of the N bits of data have different values.
6 . The semiconductor device of claim 1 , wherein the plurality of channel layers include a first channel layer, a second channel layer, and a third channel layer, the plurality of dielectric layers include a first dielectric layer surrounding the first channel layer, a second dielectric layer surrounding the second channel layer, and a third dielectric layer surrounding the third channel layer, the first dielectric layer has first coercive voltages, the second dielectric layer has second coercive voltages, and the third dielectric layer has third coercive voltages, and a magnitude of the first coercive voltages is smaller than a magnitude of the second coercive voltages and the magnitude of the second coercive voltages is smaller than a magnitude of the third coercive voltages.
7 . The semiconductor device of claim 6 , wherein the peripheral circuit region is configured to apply a first program voltage to the gate electrode of a selected memory element in a program operation of writing first data to a selected one of the plurality of memory elements, and the first program voltage is greater than or equal to a third positive coercive voltage of the third coercive voltages.
8 . The semiconductor device of claim 7 , wherein the peripheral circuit region is configured to sequentially apply the first program voltage and a second program voltage to the gate electrode of the selected memory element, and a magnitude of the second program voltage is equal to or greater than a magnitude of a first negative coercive voltage of the first coercive voltages and lower than a magnitude of a second negative coercive voltage of the second coercive voltages.
9 . The semiconductor device of claim 7 , wherein the peripheral circuit region is configured to sequentially apply the first program voltage and a second program voltage to the gate electrode of the selected memory element, and a magnitude of the second program voltage is equal to or greater than a magnitude of a second negative coercive voltage of the second coercive voltages and lower than a magnitude of a third negative coercive voltage of the third coercive voltages.
10 . The semiconductor device of claim 6 , wherein the peripheral circuit region is configured to program each of the plurality of memory elements to have one of first to eighth states.
11 . The semiconductor device of claim 1 , wherein each of the plurality of dielectric layers has a different coercive voltage.
12 . The semiconductor device of claim 1 , wherein each of the plurality of dielectric layers has a different thickness.
13 . A semiconductor device comprising: a memory cell array including a plurality of memory elements; and a peripheral circuit region including peripheral circuits configured to control the memory cell array, wherein each of the plurality of memory elements includes an active region extending in a first direction, a gate electrode intersecting the active region, the gate electrode extending in a second direction, a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the active region, and the plurality of channel layers surrounded by the gate electrode, and a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and wherein the peripheral circuit region is configured to sequentially apply a first program voltage and a second program voltage to the gate electrode of a selected memory element in a program operation of writing first data to a selected one of the plurality of memory elements, and the first program voltage has a different sign than the second program voltage.
14 . The semiconductor device of claim 13 , wherein the first program voltage has a different magnitude than the second program voltage.
15 . The semiconductor device of claim 13 , wherein each of the plurality of dielectric layers has a different coercive voltage.
16 . The semiconductor device of claim 13 , wherein each of the plurality of dielectric layers has a different thickness.
17 . A semiconductor device comprising: a memory cell array including a plurality of memory elements; and a peripheral circuit region including peripheral circuits configured to control the memory cell array, wherein each of the plurality of memory elements includes a substrate including an active region extending in a first direction; a gate electrode on the substrate, the gate electrode extending in a second direction and intersecting the active region; a first channel layer, a second channel layer, and a third channel layer spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the substrate, wherein the first channel layer, the second channel layer and the third channel layer are sequentially stacked on the active region, and wherein the first channel layer, the second channel layer and the third channel layer are surrounded by the gate electrode; a first dielectric layer surrounding the first channel layer, a second dielectric layer surrounding the second channel layer, and a third dielectric layer surrounding the third channel layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially stacked in the third direction on the active region, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer include at least one of a ferroelectric material or an anti-ferroelectric material; and source/drain regions in recess regions in which the active region is recessed, the source/drain regions on both sides of the gate electrode, and the source/drain regions in contact with the first channel layer, the second channel layer and the third channel layer, and wherein the peripheral circuit region is configured to apply a first program voltage to the gate electrode of a selected memory element in a program operation of writing first data to a selected one of the plurality of memory elements, and the first program voltage is determined based on coercive voltages of the first dielectric layer, the second dielectric layer, and the third dielectric layer.
18 . The semiconductor device of claim 17 , wherein the first dielectric layer has first coercive voltages, the second dielectric layer has second coercive voltages, and the third dielectric layer has third coercive voltages, a magnitude of the first coercive voltages is smaller than a magnitude of the second coercive voltages, and the magnitude of the second coercive voltages is smaller than a magnitude of the third coercive voltages, and a magnitude of the first program voltage is greater than or equal to a magnitude of the third coercive voltages.
19 . The semiconductor device of claim 17 , wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer has a different thickness.
20 . The semiconductor device of claim 17 , wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer has a different coercive voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of and claims the benefit of priority to U.S. Patent Application No. 18/069,398, filed December 21, 2022, which claims the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 10-2022-0026255 filed on February 28, 2022 and Korean Patent Application No. 10-2022-0043530 filed on April 7, 2022 in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference. FIELD The present inventive concept relates to a semiconductor device. BACKGROUND Ferroelectrics are materials having ferroelectricity that maintains spontaneous polarization by aligning internal electric dipole moments even when no external electric field is applied. Research has been conducted to apply such ferroelectric properties to memory elements of semiconductor devices. SUMMARY Some example embodiments provide a semiconductor device having improved integration and electrical characteristics. According to some example embodiments, a semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate, the gate electrode extending in a second direction and intersecting the active region, and a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the substrate, and the plurality of channel layers surrounded by the gate electrode. The device includes a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers having a different coercive voltage, and source/drain regions in recess regions in which the active region is recessed, the source/drain regions on both sides of the gate electrode, and the source/drain regions in contact with the plurality of channel layers. According to some example embodiments, a semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate, the gate electrode extending in a second direction and intersecting the active region, and a first channel layer, a second channel layer, and a third channel layer spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the substrate, wherein the first channel layer, the second channel layer and the third channel layer are sequentially stacked on the active region, and wherein the first channel layer, the second channel layer and the third channel layer are surrounded by the gate electrode. The device includes a first dielectric layer surrounding the first channel layer, a second dielectric layer surrounding the second channel layer, and a third dielectric layer surrounding the third channel layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially stacked in the third direction on the active region, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer include at least one of a ferroelectric material or an anti-ferroelectric material, and wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer has a different thickness. The device includes source/drain regions in recess regions in which the active region is recessed, the source/drain regions on both sides of the gate electrode, and the source/drain regions in contact with the first channel layer, the second channel layer and the third channel layer. According to some example embodiments, a semiconductor device includes a memory cell array including a plurality of memory elements, and a peripheral circuit region including peripheral circuits configured to control the memory cell array. Each of the plurality of memory elements includes an active region extending in a first direction, a gate electrode intersecting the active region, the gate electrode extending in a second direction, a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the active region, and the plurality of channel layers surrounded by the gate electrode, and a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material. In each of the plurality of memory elements, a number of the plurality of channel layers is N, where N is a natural number equal to or greater than 2, and each of the plurality of memory elements is configured to store N bits of data or less. BRIEF DESCRIPTION OF DRAWIN