US-20260129865-A1 - Memory and Preparation Method Thereof, and Electronic Device

Abstract

A memory includes a substrate, a plurality of memory arrays, a filling structure, and an isolation spacer. The memory array includes a plurality of memory cells. Each memory cell includes a transistor and at least one capacitor that are stacked, and the at least one capacitor is electrically connected to a side of the transistor distal from the substrate. The filling structure is disposed between transistors of two adjacent memory arrays. The isolation spacer is disposed on a side of the filling structure distal from the substrate and in a direction parallel to the substrate positioned between capacitors of the two adjacent memory arrays.

Inventors

• Shihui Yin
• Weiliang Jing
• Bingwu JI
• Zhengbo WANG
• Heng Liao

Assignees

• HUAWEI TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20260105

Priority Date

20230707

Claims (20)

1. 1 . A memory, comprising: a substrate; and a plurality of memory arrays disposed on the substrate, wherein each of the memory arrays comprises a plurality of memory cells, and wherein each of the memory cells comprises: a transistor and at least one capacitor stacked in a first direction perpendicular to the substrate, wherein the at least one capacitor is electrically connected to a side of the transistor distal from the substrate; a filling structure disposed on the substrate, wherein the filling structure comprises a virtual transistor spaced apart from the transistor, wherein at least a part of a film layer of the virtual transistor and at least a part of a film layer of the transistor are disposed at a same film layer, and wherein the filling structure is positioned in a second direction parallel to the substrate between transistors of two adjacent memory arrays; and an isolation spacer disposed on a side of the filling structure distal from the substrate, wherein the isolation spacer is positioned in the second direction between capacitors of the two adjacent memory arrays.
2. 2 . The memory of claim 1 , wherein the transistor comprises: a first electrode electrically connected to the at least one capacitor and disposed in the first direction; a second electrode disposed in the first direction; a first channel layer disposed between the first electrode and the second electrode; and a first gate surrounding the first channel layer.
3. 3 . The memory of claim 2 , wherein the virtual transistor comprises: a third electrode disposed in the first direction and connected to the isolation spacer; a fourth electrode disposed in the first direction; a second channel layer disposed between the first electrode and the second electrode; and a second gate surrounding the second channel layer, wherein the first electrode of each transistor and the third electrode of each virtual transistor are disposed at a same film layer, wherein each channel layer of each transistor and each channel layer of each virtual transistor are disposed at a same channel layer, and wherein the first gate of each transistor and the second gate of each virtual transistor are disposed at a same film layer.
4. 4 . The memory of claim 3 , wherein the memory cells are spaced from each other in a second direction, wherein the memory cells are spaced from each other in a third direction, wherein the second direction and the third direction are both perpendicular to the first direction, wherein the second direction intersects with the third direction, and wherein the memory further comprises: a plurality of conducting wires that are spaced from each other in the third direction, wherein an extension direction of the conducting wires is parallel to the second direction, wherein each of the conducting wires comprises a conducting portion and a dielectric portion that are alternately disposed in the second direction, wherein the conducting portion and the second electrode are disposed at a same film layer and are in contact, and wherein the dielectric portion and the second electrode are disposed at a same film layer and are in contact; and a plurality of bit lines that are spaced from each other in the third direction, wherein each of the bit lines is disposed between one of the conducting wires and the substrate, wherein an extension direction of the bit lines is parallel to the second direction, and wherein each of the bit lines is electrically connected to the conducting portion of one of the conducting wires.
5. 5 . The memory of claim 4 , wherein the memory cells are spaced from each other in the second direction, wherein the memory cells are spaced from each other in the third direction, wherein the second direction and the third direction are both perpendicular to the first direction, wherein the second direction intersects with the third direction, wherein the memory further comprises a plurality of virtual transistors between the two adjacent memory arrays, wherein the virtual transistors are spaced from each other in the third direction, and wherein the virtual transistors and a plurality of transistors arranged in the second direction are spaced from each other in the second direction.
6. 6 . The memory of claim 5 , wherein each row of the virtual transistors that are arranged in the third direction constitutes a virtual transistor group disposed between the two adjacent memory arrays, and wherein the virtual transistor groups are spaced from each other in the second direction.
7. 7 . The memory of claim 6 , wherein a distance between the virtual transistors and the transistors that are arranged in the second direction and that are adjacent to each other is equal to a distance between two transistors that are arranged in the second direction and that are adjacent to each other.
8. 8 . The memory of claim 7 , wherein a distance between two virtual transistors that are arranged in the second direction and that are adjacent to each other is equal to the distance between the two transistors that are arranged in the second direction and that are adjacent to each other.
9. 9 . The memory of claim 7 , wherein the memory further comprises a plurality of word lines that are spaced from each other in the second direction, wherein an extension direction of the word lines is parallel to the third direction, wherein at least one word line is electrically connected to gates of the plurality of transistors arranged in the third direction, and wherein at least one word line is electrically connected to gates of the plurality of virtual transistors arranged in the third direction.
10. 10 . The memory of claim 1 , wherein the filling structure comprises a support block, and wherein a material of the support block comprises an insulating material.
11. 11 . The memory of claim 1 , wherein the memory further comprises insulating portions disposed between the filling structures and the memory arrays and between the isolation spacers and the memory arrays, and wherein the insulating portions and the filling structures comprise different materials.
12. 12 . The memory of claim 1 , wherein the at least one capacitor is a ferroelectric capacitor.
13. 13 . A memory preparation method, comprising: providing a substrate; forming a plurality of memory arrays and a filling structure on the substrate, wherein each of the memory arrays comprises a plurality of memory cells, wherein each of the memory cells comprises a transistor and at least one capacitor stacked in a first direction perpendicular to the substrate, wherein the at least one capacitor is electrically connected to a side of the transistor distal from the substrate, wherein the filling structure comprises a virtual transistor positioned in a second direction parallel to the substrate and between two adjacent memory arrays, and wherein at least a part of film layers of the virtual transistor and at least a part of film layers of the transistor are disposed at a same film layer; and forming an isolation spacer disposed on a side of the filling structure distal from the substrate and positioned in the second direction between the two adjacent memory arrays.
14. 14 . The memory preparation method of claim 13 , wherein after providing the substrate and before forming the plurality of memory arrays and the filling structure, the memory preparation method further includes: forming a plurality of bit lines spaced from each other in a third direction that is perpendicular to the first direction and intersects with the second direction; forming a plurality of intermediate conducting wires spaced from each other in the third direction, wherein each of the intermediate conducting wires is disposed on a side of a bit line distal from the substrate, and wherein extension directions of the bit lines and the intermediate conducting wires are parallel to a second direction; removing a part of each of the intermediate conducting wires to form a plurality of grooves, wherein each of the intermediate conducting wires between grooves constitutes a conducting portion; forming a dielectric portion in each of the grooves, wherein a plurality of dielectric portions and a plurality of conducting portions alternately disposed in the second direction constitute a conducting wire; and forming a plurality of word lines spaced from each other in the second direction, wherein each of the word lines is disposed on a side of the conducting wire distal from the substrate, and wherein an extension direction of each of the word lines is parallel to the third direction.
15. 15 . The memory preparation method of claim 14 , further comprising: forming second electrodes of the transistors when the conducting portions are formed; forming second electrodes of the virtual transistors when the dielectric portions are formed in the grooves; and forming first metal gate of the transistors and a second metal gate of the virtual transistors when the word lines that are spaced from each other in the second direction are formed.
16. 16 . The memory preparation method of claim 15 , wherein forming the plurality of memory arrays and the filling structure comprises: forming a first channel hole and a second channel hole that pass through each of the word lines; filling the first channel hole with a gate medium material and a channel material to form a first gate medium layer of the transistor and a first channel layer of the transistor in the first channel hole, wherein the first metal gate and the first gate medium layer constitute a first gate of the transistor; filling the second channel hole with a gate medium material and a channel material to form a second gate medium layer of the virtual transistor and a second channel layer of the virtual transistor in the second channel hole, wherein the first gate the first gate medium layer constitute the first gate of the transistor, wherein a second gate of the virtual transistor surrounds the second channel layer, wherein the second gate and the second gate medium layer constitute the second gate, and wherein the second gate surrounds the second channel layer; and forming a first electrode of the transistor and a second electrode of the virtual transistor, wherein the first electrode is disposed on a side of the first channel layer of the transistor distal from the substrate, and wherein the second electrode is disposed on a side of the second channel layer of the virtual transistor distal from the substrate.
17. 17 . The memory preparation method of claim 16 , wherein forming the plurality of memory arrays further comprises: forming a plurality of dielectric layers and a plurality of conducting layers that are alternately stacked; forming a through hole that passes through the plurality of dielectric layers and the plurality of conducting layers; and sequentially filling the through hole with a capacitor material and an electrode material to form a capacitor layer and a capacitor electrode in the through hole, wherein the capacitor layer is disposed between the capacitor electrode and a side wall of the through hole, wherein the capacitor electrode is a shared second capacitor electrode of a plurality of capacitors, and wherein at least a part of the conducting layers surround a periphery of the capacitor layer and define a first capacitor electrode of a capacitor.
18. 18 . The memory preparation method of claim 17 , wherein forming the isolation spacer comprises: forming a filling space that passes through the plurality of dielectric layers and the plurality of conducting layers; and filling the filling space with an isolation material to form the isolation spacer.
19. 19 . An electronic device, comprising: a processor; and a memory electrically connected to the processor, and comprising: a substrate; a plurality of memory arrays disposed on the substrate, wherein each memory array comprises a plurality of memory cells, and wherein each memory cell comprises: a transistor and at least one capacitor stacked in a first direction perpendicular to the substrate, wherein the at least one capacitor is electrically connected to a side of the transistor distal from the substrate; a filling structure disposed on the substrate, wherein the filling structure comprises a virtual transistor positioned in a second direction parallel to the substrate between transistors of two adjacent memory arrays, wherein at least a part of a film layer of the virtual transistor and at least a part of a film layer of the transistor are disposed at a same film layer, and wherein the virtual transistor and the transistor are spaced apart from each other; and an isolation spacer disposed on a side of the filling structure distal from the substrate, wherein the isolation spacer is positioned in the second direction between capacitors of the two adjacent memory arrays.
20. 20 . The electronic device of claim 19 , wherein the transistor comprises: a first electrode electrically connected to the at least one capacitor and disposed in the first direction; a second electrode disposed in the first direction; a first channel layer disposed between the first electrode and the second electrode; and a first gate surrounding the first channel layer; and wherein the virtual transistor comprises: a third electrode disposed in the first direction and connected to the isolation spacer; a fourth electrode disposed in the first direction; a second channel layer disposed between the first electrode and the second electrode; and a second gate surrounding the second channel layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/CN2024/080935, filed on Mar. 11, 2024, which claims priority to Chinese Patent Application No. 202310834326.3, filed on Jul. 7, 2023. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties. TECHNICAL FIELD This disclosure relates to the field of semiconductor storage technologies, and in particular, to a memory and a preparation method thereof, and an electronic device. BACKGROUND With explosive development of information, higher storage density is a development direction of storage technologies, to obtain a higher storage capacity. As a result, a three-dimensional (3D) memory merges. The three-dimensional memory usually includes a plurality of memory arrays for storing data, and the memory arrays are stacked in a direction perpendicular to a substrate to form a 3D structure. The memory array may include a plurality of memory cells, and each memory cell includes a metal-oxide-semiconductor field-effect transistor (MOSFET) and at least one capacitor electrically connected to the transistor. However, in a memory cell located at an edge of a memory array in a related technology, a transistor is prone to performance degradation. SUMMARY Embodiments of this disclosure provide a memory and a preparation method thereof, and an electronic device, to mitigate a phenomenon that a transistor in a memory cell located at an edge of a memory array is prone to performance degradation. To achieve the foregoing objective, the following technical solutions are used in embodiments of this disclosure. According to a first aspect, a memory is provided. The memory includes a substrate, a plurality of memory arrays, a filling structure, an insulating portion, and an isolation spacer. The plurality of memory arrays are located on the substrate, the memory array includes a plurality of memory cells, the memory cell includes a transistor and at least one capacitor that are stacked in a first direction, the at least one capacitor is electrically connected to a side that is of the transistor and that is away, or distal, from the substrate, and the first direction is perpendicular to the substrate. The filling structure is located on the substrate, and in a direction parallel to the substrate, the filling structure is located between transistors of two adjacent memory arrays. The isolation spacer is located on a side that is of the filling structure and distal from the substrate, and in the direction parallel to the substrate, the isolation spacer is located between capacitors of the two adjacent memory arrays. During preparation of the memory array, processes such as etching and chemical mechanical polishing (CMP) are required to prepare the transistor. It may be understood that structures of the transistors of the plurality of memory arrays need to be synchronously prepared by using these processes. Because there is a great difference between structure density of an isolation region and structure density of an edge region, during the foregoing preparation process, a process defect may occur in a film layer structure located in the edge region (for example, the film layer structure is dented and deformed), resulting in performance degradation of a transistor located in the edge region. Herein, the “isolation region” refers to a region located between adjacent memory arrays, and the “edge region” refers to a region located at an edge of the memory array. Herein, the “structure density” refers to a quantity of transistors in a unit area of such region. Herein, the “performance degradation” refers to a phenomenon like an excessively high off-state current of the transistor. The filling structure is disposed between the two adjacent memory arrays, to increase structure density of the isolation region, thereby reducing a difference between the structure density of the edge region of the memory array and the structure density of the isolation region. In this way, during the preparation process, the process defect of the film layer structure in the edge region of the memory array can be mitigated, thereby mitigating a performance degradation phenomenon of the transistor in the edge region of the memory array. In some implementations, the filling structure includes a virtual transistor, at least a part of the virtual transistor and at least a part of the transistor are disposed at a same layer, and the virtual transistor and the transistor are spaced from each other. This helps simplify a preparation process of the filling structure, improves preparation efficiency of the memory, and reduces preparation costs of the memory. In addition, a dielectric portion of a conducting wire and a second electrode of the virtual transistor are disposed at a same layer, so that the virtual transistor does not have a control function. This helps prevent the virtual transistor from interfering with ano