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US-20260129866-A1 - SOT MRAM HAVING DIELECTRIC INTERFACIAL LAYER AND METHOD FORMING SAME

US20260129866A1US 20260129866 A1US20260129866 A1US 20260129866A1US-20260129866-A1

Abstract

A method includes depositing a plurality of layers, which includes depositing a spin orbit coupling layer, depositing a dielectric layer over the spin orbit coupling layer, depositing a free layer over the dielectric layer, depositing a tunnel barrier layer over the free layer, and depositing a reference layer over the tunnel barrier layer. The method further includes performing a first patterning process to pattern the plurality of layers, and performing a second patterning process to pattern the reference layer, the tunnel barrier layer, the free layer, and the dielectric layer. The second patterning process stops on a top surface of the spin orbit coupling layer.

Inventors

  • Wilman Tsai
  • Mingyuan SONG
  • Shy-Jay Lin

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260507
Application Date
20251218

Claims (20)

  1. 1 . A method comprising: applying a voltage to a spin orbit coupling layer to program a Magnetic Tunnel Junction (MTJ) cell, wherein the spin orbit coupling layer is over a dielectric seed layer, and wherein the MTJ cell comprises: a dielectric layer over the spin orbit coupling layer; a free layer over the dielectric layer; a tunnel barrier layer over the free layer; and a reference layer over the tunnel barrier layer, wherein a spin polarized current is generated in the spin orbit coupling layer in response to the voltage, and wherein the spin polarized current flows through the dielectric layer and into the free layer to program the free layer.
  2. 2 . The method of claim 1 , wherein the spin polarized current that flows into the free layer flows back into the spin orbit coupling layer.
  3. 3 . The method of claim 1 , wherein the voltage is applied to a first end and a second end of the spin orbit coupling layer, and wherein the first end and the second end are opposite ends of the spin orbit coupling layer.
  4. 4 . The method of claim 3 , wherein the applying the voltage comprises connecting the first end and the second end to a positive power supply voltage VDD and an electrical ground, respectively.
  5. 5 . The method of claim 1 , wherein the spin orbit coupling layer extends laterally beyond edges of the dielectric layer toward opposite lateral directions.
  6. 6 . The method of claim 1 , wherein the MTJ cell further comprises a top electrode over the reference layer, and wherein when the MTJ cell is programmed, the top electrode is disconnected from any voltage source and current source.
  7. 7 . The method of claim 1 further comprising reading the MTJ cell comprising: applying an additional voltage between a top electrode of the MTJ cell and the spin orbit coupling layer; and measuring a current flowing through the MTJ cell to determine a state of the MTJ cell.
  8. 8 . The method of claim 7 , wherein the state of the MTJ cell is selected from a high-resistance state and a low-resistance state.
  9. 9 . The method of claim 1 , wherein the free layer and the reference layer are formed of ferromagnetic materials.
  10. 10 . The method of claim 1 , wherein the dielectric seed layer has a crystalline structure.
  11. 11 . The method of claim 1 , wherein the dielectric seed layer comprises MgO.
  12. 12 . A method comprising: applying a voltage to a memory cell over a dielectric seed layer to perform an operation on the memory cell, wherein the operation is selected from a program operation and a read operation, and wherein the memory cell comprises: a metal layer over and contacting the dielectric seed layer, wherein the dielectric seed layer extends laterally beyond a corresponding edge of the metal layer; a dielectric layer over the metal layer; a free layer over and contacting the dielectric layer; a tunnel barrier layer over the free layer; a reference layer over the tunnel barrier layer; and a top electrode over the reference layer.
  13. 13 . The method of claim 12 , wherein the operation is the program operation, and wherein the voltage is applied to opposite ends of the metal layer.
  14. 14 . The method of claim 12 , wherein the program operation is configured to change a state of the memory cell.
  15. 15 . The method of claim 12 , wherein the operation is the read operation, and wherein the voltage is applied between the top electrode and the metal layer.
  16. 16 . The method of claim 12 , wherein the dielectric seed layer comprises a metal oxide.
  17. 17 . The method of claim 16 , wherein the metal oxide comprises MgO that has a crystalline structure.
  18. 18 . A method comprising: providing a memory cell structure comprising: a first dielectric layer having a crystalline structure; a metal layer over and contacting the first dielectric layer; a second dielectric layer over the metal layer; a free layer over the second dielectric layer; a tunnel barrier layer over the free layer; and a reference layer over the tunnel barrier layer; and connecting a first end and a second end of the metal layer to a positive voltage and an electrical ground, respectively, to program the memory cell structure.
  19. 19 . The method of claim 18 , wherein the first dielectric layer comprises a metal oxide.
  20. 20 . The method of claim 18 further comprising reading the memory cell structure by determining a resistance of the memory cell structure based on a current flowing through the memory cell structure, wherein the current is generated by the positive voltage.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 18/774,254, entitled “SOT MRAM HAVING DIELECTRIC INTERFACIAL LAYER AND METHOD FORMING SAME,” and filed Jul. 16, 2024, which is a continuation of U.S. patent application Ser. No. 17/809,928, entitled “8SOT MRAM Having Dielectric Interfacial Layer and Method Forming Same,” and filed Jun. 30, 2022, which is now U.S. Pat. No. 12,114,510, issued Oct. 8, 2024, which is a divisional of U.S. patent application Ser. No. 16/806,203, entitled “SOT MRAM Having Dielectric Interfacial Layer and Method Forming Same,” and filed Mar. 2, 2020, now U.S. Pat. No. 11,469,267, issued Oct. 11, 2022, which claims the benefit of the U.S. Provisional Application No. 62/849,322, entitled “SOT MRAM Having Dielectric Interfacial Layer and Method Forming Same,” and filed May 17, 2019, which applications are hereby incorporated herein by reference. BACKGROUND Semiconductor memories are used in integrated circuits for electronic applications, including cell phones and personal computing devices, as examples. One type of semiconductor memory device is Magneto-Resistive Random Access Memory (MRAM), which involves spin electronics that combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, rather than the charge of the electrons, are used to store bit values. Conventional MRAM cells are Spin-Transfer Torque (STT) MRAM cells. A typical STT MRAM cell may include a Magnetic Tunnel Junction (MTJ) stack, which includes a pinning layer, a pinned layer over the pinning layer, a tunnel layer over the pinned layer, and a free layer over the tunnel layer. During the formation of the MRAM cell, a plurality of blanket layers are deposited first. The blanket layers are then patterned through a photo etching process to form the MTJ stack. A dielectric capping layer is then formed to protect the MTJ stack. The dielectric capping layer includes some portions on the sidewalls, and possibly additional portions over the top surface, of the MTJ stack. The STT MRAM cells suffer from reliability problem due to the fact that programming currents have to pass through the tunnel layer, hence degrade or damage the tunnel layer. Accordingly, Spin Orbit Torque (SOT) MRAM was developed. In the programming of the SOT MRAM cells, the programming current does not pass through the tunnel layer, hence the reliability of the SOT MRAM is improved over the STT MRAM. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1 through 10 illustrate the cross-sectional views and a top view of intermediate stages in the formation of a Spin Orbit Torque (SOT) Magneto-Resistive Random Access Memory (MRAM) cell in accordance with some embodiments. FIG. 11 illustrates the cross-sectional view of an in-plane SOT MRAM cell in accordance with some embodiments. FIG. 12 illustrates the writing (programming) operation of an SOT MRAM cell in accordance with some embodiments. FIG. 13 illustrates the reading operation of an SOT MRAM cell in accordance with some embodiments. FIGS. 14 and 15 illustrate the comparison of the results of several SOT MRAM cells having different materials inserted between the corresponding spin orbit coupling layers and free layers in accordance with some embodiments. FIG. 16 illustrates a process flow for forming a SOT MRAM cell in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another ele