US-20260129867-A1 - MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME

US20260129867A1US 20260129867 A1US20260129867 A1US 20260129867A1US-20260129867-A1

Abstract

A method for fabricating a magnetoresistive random access memory (MRAM) device includes first providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, using a first patterned mask to remove the first IMD layer for forming a first via opening on the MRAM region and a second via opening on the logic region, forming a metal nitride layer in the first via opening and the second via opening, removing part of the metal nitride layer and part of the first IMD layer on the logic region for forming a trench opening, and forming a metal layer in the first via opening, the second via opening, and the trench opening for forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region.

Inventors

Hui-Lin WANG
Ching-Hua Hsu
Chen-Yi Weng
Che-wei Chang

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260507
Application Date: 20241202
Priority Date: 20241101

Claims (17)

1 . A method for fabricating a magnetoresistive random access memory (MRAM) device, comprising: providing a substrate having a MRAM region and a logic region; forming a first inter-metal dielectric (IMD) layer on the substrate; using a first patterned mask to remove the first IMD layer for forming a first via opening on the MRAM region and a second via opening on the logic region; forming a metal nitride layer in the first via opening and the second via opening; removing part of the metal nitride layer and part of the first IMD layer on the logic region for forming a trench opening; forming a metal layer in the first via opening, the second via opening, and the trench opening for forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region; and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.
2 . The method of claim 1 , further comprising: forming a hard mask on the first IMD layer; using the first patterned mask to remove the hard mask and the first IMD layer for forming the first via opening on the MRAM region and the second via opening on the logic region; forming the metal nitride layer in the first via opening and the second via opening; using a second patterned mask to remove part of the metal nitride layer and part of the first IMD layer on the logic region for forming the trench opening; forming the metal layer in the first via opening, the second via opening, and the trench opening; and planarizing the metal layer for forming the first metal interconnection on the MRAM region and the second metal interconnection on the logic region.
3 . The method of claim 2 , wherein the first metal interconnection comprises a first via conductor.
4 . The method of claim 3 , wherein the first via conductor comprises: the metal nitride layer; a barrier layer on the metal nitride layer; and the metal layer on the barrier layer.
5 . The method of claim 2 , wherein the second metal interconnection comprises: a second via conductor; and a trench conductor on the second via conductor.
6 . The method of claim 5 , wherein the second via conductor comprises: the metal nitride layer; a barrier layer on the metal nitride layer; and the metal layer on the barrier layer.
7 . The method of claim 5 , wherein the trench conductor comprises: a barrier layer; and the metal layer on the barrier layer.
8 . The method of claim 1 , further comprising: forming a second IMD layer on the first IMD layer; forming a third metal interconnection on the first metal interconnection; and forming the MTJ on the third metal interconnection.
9 . The method of claim 8 , wherein the third metal interconnection comprises a via conductor.
10 . The method of claim 1 , wherein the metal nitride layer comprises titanium nitride (TiN).
11 . A magnetoresistive random access memory (MRAM) device, comprising: a substrate having a MRAM region and a logic region; a first inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the first IMD layer on the MRAM, wherein the first metal interconnection comprises a first via conductor; a second metal interconnection in the first IMD layer on the logic region, wherein the second metal interconnection comprises: a second via conductor; a trench conductor on the second via conductor, wherein the second via conductor and the trench conductor comprise different materials; and a magnetic tunneling junction (MTJ) on the first metal interconnection.
12 . The MRAM device of claim 11 , further comprising: a second IMD layer on the first IMD layer; a third metal interconnection on the first metal interconnection; and the MTJ on the third metal interconnection.
13 . The MRAM device of claim 12 , wherein the third metal interconnection comprises a third via conductor.
14 . The MRAM device of claim 12 , further comprising: a third IMD layer on the second IMD layer and around the MTJ; a fourth metal interconnection on the second metal interconnection.
15 . The MRAM device of claim 14 , wherein the fourth metal interconnection comprises: a fourth via conductor; and a second trench conductor on the fourth via conductor.
16 . The MRAM device of claim 11 , wherein the second via conductor comprises: a metal nitride layer; a barrier layer on the metal nitride layer; and a metal layer on the barrier layer.
17 . The MRAM device of claim 11 , wherein the trench conductor comprises: a barrier layer; and a metal layer on the barrier layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a magnetoresistive random access memory (MRAM) and method for fabricating the same. 2. Description of the Prior Art Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source. The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a method for fabricating a magnetoresistive random access memory (MRAM) device includes first providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, using a first patterned mask to remove the first IMD layer for forming a first via opening on the MRAM region and a second via opening on the logic region, forming a metal nitride layer in the first via opening and the second via opening, removing part of the metal nitride layer and part of the first IMD layer on the logic region for forming a trench opening, and forming a metal layer in the first via opening, the second via opening, and the trench opening for forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region. According to another aspect of the present invention, a magnetoresistive random access memory (MRAM) device includes a substrate having a MRAM region and a logic region, a first inter-metal dielectric (IMD) layer on the substrate, a first metal interconnection in the first IMD layer on the MRAM, a second metal interconnection in the first IMD layer on the logic region, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the first metal interconnection includes a first via conductor and the second metal interconnection includes a second via conductor and a trench conductor on the second via conductor, in which the second via conductor and the trench conductor include different materials. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-9 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. FIG. 10 illustrates a structural view of a MRAM device according to an embodiment of the present invention. DETAILED DESCRIPTION Referring to FIGS. 1-9, FIGS. 1-9 illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12 made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region 14 and a logic region 16 are defined on the substrate 12. Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer 18 could also be formed on top of the substrate 12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate 12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer 18 could be formed on the substrate 12 to cover the MOS transistors, and a plurality of contact plugs could