US-20260129869-A1 - ELECTRONIC CHIP COMPRISING A MEMORY CIRCUIT

US20260129869A1US 20260129869 A1US20260129869 A1US 20260129869A1US-20260129869-A1

Abstract

A memory circuit of a chip includes: an interconnection stack and several memory cells, each including a memory element above the stack and a selection transistor formed in the substrate and including a first node. Each element includes a first electrode, a layer form by an OTS material, and a second electrode connected to the layer on opposite side with respect to the first electrode. In each cell, the first node of the transistor is connected to the element via a conductive via extending through an entire thickness of the stack. The memory circuit further includes a control circuit configured to apply, between the first and the second electrodes of each element, first or second voltage impulses of respectively first or second opposite polarities to set respectively first or second logic states of the element.

Inventors

Andrea Redaelli
Roberto Annunziata

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260507
Application Date: 20251106
Priority Date: 20241107

Claims (17)

1 . An electronic chip including a memory circuit, comprising: a semiconductor substrate; an interconnection stack arranged on the semiconductor substrate; and a plurality of memory cells, wherein each memory cell comprises a memory element arranged above the interconnection stack and a selection transistor formed in the semiconductor substrate and comprising a first conduction node; wherein each memory element comprises a first electrode, an intermediate layer comprising an ovonic threshold switching material, and a second electrode connected to the intermediate layer on opposite side with respect to the first electrode; wherein, in each memory cell, the first conduction node of the selection transistor is connected to the memory element via a respective conductive via extending through an entire thickness of the interconnection stack; and wherein the memory circuit further comprises a control circuit structured and configured to apply, between the first electrode and the second electrode of each memory element, a first voltage impulse of a first polarity to set a first logic state of the memory element and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the memory element.
2 . The electronic chip according to claim 1 , wherein the intermediate layer is made of a chalcogenide material and wherein the second electrode comprises a resistor electrically contacting the intermediate layer.
3 . The electronic chip according to claim 1 , wherein the memory cells are organized in an array of bit lines and word lines and wherein each memory cell is connected to a respective bit line by its first electrode and to a respective word line by its second electrode.
4 . The electronic chip according to claim 3 , wherein each transistor comprises a gate which is connected to a respective word line, and a second conduction node connected to ground.
5 . The electronic chip according to claim 1 , wherein the memory cells are free of any phase change material.
6 . The electronic chip according to claim 1 , wherein the conductive via is made of a metallic material.
7 . The electronic chip according to claim 1 , wherein the interconnection stack has a thickness in a range from 100 nm to 600 nm.
8 . The electronic chip according to claim 1 : wherein the interconnection stack comprises a plurality of levels, each level comprising a first insulating layer and a second insulating layer; and wherein the first insulating layer is made of a material selected from the group consisting of: SiOC, porous SiOC, SiOCH, or porous SiOCH, and has a thickness in the range from 30 nm to 110 nm; and wherein the second insulating layer is made of a material selected from the group consisting of: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN and has a thickness in the range from 2 nm to 50 nm.
9 . The electronic chip according to claim 1 , comprising: a third insulating layer interposed between the interconnection stack and the memory element, wherein the third insulating layer is made of a material selected from the group consisting of: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN and has a thickness in the range from 2 nm to 50 nm; and a fourth insulating layer interposed between the third insulating layer and the memory element, and wherein the fourth insulating layer is made of SiO 2 , and has a thickness in the range from 10 nm to 50 nm.
10 . The electronic chip according to claim 1 , wherein, for each memory element, the respective conductive via is in single piece forming an integral, unitary, conductive via body extending through the entire thickness of the interconnection stack.
11 . The electronic chip according to claim 1 , further comprising: an additional insulating layer interposed between the semiconductor substrate and the interconnection stack; and for each memory element, a respective further via extending through an entire thickness of the additional insulating layer and directly connecting the selection transistor to the respective conductive via.
12 . The electronic chip according to claim 1 , wherein the conductive via is directly connected to the second electrode of the memory element.
13 . The electronic chip according to claim 1 , wherein the selection transistor is a fin field-effect transistor.
14 . A method of manufacturing an electronic chip including a memory circuit, comprising the following successive steps: a) forming selection transistors, comprising a first conduction node, in a semiconductor substrate; b) forming an interconnection stack arranged on the semiconductor substrate; and c) forming a plurality of memory elements arranged above the interconnection stack, each memory element comprising a first electrode, an intermediate layer comprising an ovonic threshold switching material, and a second electrode connected to the intermediate layer on opposite side with respect to the first electrode; wherein the first conduction node of the selection transistor of each memory cell is connected to the memory element via a respective conductive via extending through an entire thickness of the interconnection stack; and d) forming a control circuit structured and configured to apply, between the first electrode and the second electrode of each memory element, a first voltage impulse of a first polarity to set a first logic state of the memory element and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the memory element.
15 . The method according to claim 14 , further comprising, between steps b) and c), forming the conductive via.
16 . The method according to claim 15 , wherein forming the conductive via comprises: etching the interconnection stack to form an opening extending therethrough; and filling said opening with a metallic material.
17 . The method according to claim 14 , wherein the selection transistor is a fin field-effect transistor.

Description

PRIORITY CLAIM This application claims the priority benefit of French Application for Patent No. FR2412187, filed on November 7, 2024, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. TECHNICAL FIELD The present description relates generally to electronic chips and, in particular, to electronic chips comprising a memory circuit based on an ovonic threshold switching (OTS) material. BACKGROUND Electronic chips include both memory circuits and logic circuits. More particularly of interest are electronic chips comprising memory circuits, including memory elements arranged in array, each memory element being associated to one or more selecting transistors. This transistor is used to separately program, erase, or read each memory element. An ovonic threshold switching (OTS) material toggles between an "on" and "off" state depending on the amount of voltage potential applied across the electronic cell. The state of the ovonic threshold switch changes when a voltage through the ovonic threshold switch exceeds a threshold voltage. Once the threshold voltage is reached, the "on" state is triggered and the ovonic threshold switch is in a substantially conductive state. If the current or voltage potential drops below the threshold value, the ovonic threshold switch returns to the "off" state. It would be desirable to improve at least in part some aspects of the known electronic chips. SUMMARY In an embodiment, an electronic chip includes a memory circuit comprising: a semiconductor substrate; an interconnection stack arranged on the semiconductor substrate; and a plurality of memory cells, each memory cell comprising a memory element arranged above the interconnection stack and a selection transistor comprising a first conduction node and formed in the semiconductor substrate; wherein each memory element comprises a first electrode, an intermediate layer comprising an ovonic threshold switching material, and a second electrode connected to the intermediate layer on opposite side with respect to the first electrode; wherein, in each memory cell, the first conduction node of the selection transistor is connected to the memory element via a respective conductive via extending through an entire thickness of the interconnection stack; and wherein the memory circuit further comprises a control circuit structured and configured to apply, between the first electrode and the second electrode of each memory element, a first voltage impulse of a first polarity to set a first logic state of the memory element and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the memory element. According to an embodiment, the intermediate layer is made of a chalcogenide material and the second electrode comprises a resistor electrically contacting the intermediate layer. According to an embodiment, the memory cells are organized in an array of bit lines and word lines and each memory cell is connected to a respective bit line by its first electrode and to a respective word line by its second electrode. According to an embodiment, each transistor comprises a gate which is connected to a respective word line, and a second conduction node connected to the ground. According to an embodiment, the memory cells is free of any phase change material. According to an embodiment, the conductive via is made of a metallic material. According to an embodiment, the interconnection stack has a thickness in the range from 100 nm to 600 nm. According to an embodiment, the interconnection stack comprises a plurality of levels, each level comprising a first insulating layer and a second insulating layer, the first insulating layer is made of a material selected from the group consisting of: SiOC, porous SiOC, SiOCH, or porous SiOCH, and has a thickness in the range from 30 nm to 110 nm, and the second insulating layer is made of a material selected from the group consisting of: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN and has a thickness in the range from 2 nm to 50 nm. According to an embodiment, the electronic chip comprises: a third insulating layer interposed between the interconnection stack and the memory element, the third insulating layer being made of a material selected from the group consisting of: silicon carbonitride, silicon nitride, SiCH, SiNHC, or porous SiCN and having a thickness in the range from 2 nm to 50 nm; and a fourth insulating layer interposed between the third insulating layer and the memory element, the fourth insulating layer being made of SiO2, and having a thickness in the range from 10 nm to 50 nm. According to an embodiment, for each memory element, the respective conductive via is in single piece. According to an embodiment, the electronic chip comprises: an additional insulating layer interposed between the semiconductor substrate and the interconnection stack, and, for each memory