US-20260129870-A1 - MEMORY DEVICE AND METHOD FOR FORMING THE SAME

Abstract

A method includes forming a transistor over a substrate; and forming a resistive element over the transistor, in which forming the resistive element includes forming a bottom electrode electrically connected to a source/drain region of the transistor, forming a resistive switching layer over the bottom electrode, in which the resistive switching layer is made of metal halide; and forming a top electrode over the resistive switching layer.

Inventors

• Chia-Shuo LI
• Yu-Tien Wu
• Bo-You Chen
• I-Chih NI
• Chih-I Wu

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
• NATIONAL TAIWAN UNIVERSITY

Dates

Publication Date

20260507

Application Date

20260106

Claims (20)

1. 1 . A method, comprising: forming a transistor over a substrate; and forming a resistive element having low-resistance state and a high-resistance state over the transistor, wherein forming the resistive element comprises: forming a bottom electrode electrically connected to a source/drain region of the transistor; forming a resistive switching layer over the bottom electrode; and forming a top electrode over the resistive switching layer, wherein once the resistive element is formed, the resistive element is at a low-resistance state.
2. 2 . The method of claim 1 , wherein a metal element of the bottom electrode is detectable throughout the resistive switching layer once the resistive element is formed.
3. 3 . The method of claim 1 , wherein the bottom electrode comprises a first metal layer and a second metal layer over the first metal layer, the resistive switching layer being interfacing with the second metal layer of the bottom electrode and the top electrode.
4. 4 . The method of claim 3 , wherein the first metal layer has a greater tendency to react with the resistive switching layer than the second metal layer.
5. 5 . The method of claim 4 , wherein the first metal layer and the top electrode are made of a same material.
6. 6 . The method of claim 1 , wherein the resistive switching layer is made of metal halide.
7. 7 . The method of claim 1 , wherein the resistive switching layer is made of BiI 3 .
8. 8 . A method, comprising: forming a transistor over a substrate; and forming a resistive element over the transistor, wherein forming the resistive element comprises: forming a bottom electrode electrically connected to a source/drain region of the transistor; forming a resistive switching layer over the bottom electrode, wherein the resistive switching layer reacts with the bottom electrodes, such that once the resistive switching layer is formed, a metal element of the bottom electrode is detectable throughout the resistive switching layer along a vertical direction; and forming a top electrode over the resistive switching layer.
9. 9 . The method of claim 8 , wherein a material of the bottom electrode has a greater tendency to react with the resistive switching layer than a material of the top electrode, such that the metal element of the bottom electrode diffuse upward from a bottom surface of the resistive switching layer to reach a top surface of the resistive switching layer during forming the resistive switching layer.
10. 10 . The method of claim 8 , wherein the resistive switching layer has a 2-D material crystalline structure.
11. 11 . The method of claim 8 , wherein the bottom electrode comprises silver (Ag).
12. 12 . The method of claim 8 , wherein the bottom electrode comprises a first metal layer and a second metal layer over the first metal layer.
13. 13 . The method of claim 12 , wherein a material of the second metal layer has a greater tendency to react with the resistive switching layer than a material of the first metal layer.
14. 14 . The method of claim 12 , wherein the second metal layer is thinner than the first metal layer and the top electrode.
15. 15 . A device, comprising: a substrate; a transistor over the substrate; and a resistive memory cell electrically connected to the transistor, wherein the resistive memory cell comprises: a first bottom electrode; a second bottom electrode over the first bottom electrode; a resistive switching layer over the second bottom electrode; and a top electrode over the resistive switching layer, wherein the first bottom electrode and the top electrode are made of a first material, and the second bottom electrode is made of a second material different from the first material.
16. 16 . The device of claim 15 , wherein the resistive switching layer has a low-resistance state and a high-resistance state, and the resistive switching layer is at the low-resistance state without applying any bias to the resistive memory cell.
17. 17 . The device of claim 15 , wherein the second material of the top electrode has a greater tendency to react with the resistive switching layer than the first material of the first bottom electrode and the top electrode.
18. 18 . The device of claim 15 , wherein the second bottom electrode is a silver (Ag) layer, wherein a thickness of the silver layer is at least 20 nm.
19. 19 . The device of claim 15 , wherein the resistive switching layer has a low-resistance state and a high-resistance state, and the resistive switching layer is at the low-resistance state prior to applying any bias to the resistive memory cell.
20. 20 . The device of claim 15 , wherein the second bottom electrode is thinner than the first bottom electrode and the top electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of U.S. application Ser. No. 17/681,545, filed on Feb. 25, 2022, which is herein incorporated by references in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A and 1B illustrate schematic views of a memory device in accordance with some embodiments of the present disclosure. FIG. 1C illustrates a molecular diagram of a resistive switching layer in accordance with some embodiments of the present disclosure. FIGS. 2A and 2B illustrate schematic views of a memory device in accordance with some embodiments of the present disclosure. FIGS. 3A and 3B illustrate schematic views of a memory device in accordance with some embodiments of the present disclosure. FIG. 4 illustrates experiment results of memory devices in accordance with some embodiments of the present disclosure. FIGS. 5A, 5B and 5C are experiment results of memory devices in accordance with some embodiments of the present disclosure. FIGS. 6A and 6B are experiment results of memory devices in accordance with some embodiments of the present disclosure. FIGS. 7A and 7B are experiment results of memory devices in accordance with some embodiments of the present disclosure. FIGS. 8A and 8B are schematic views of resistive random access memory (RRAM) element in accordance with some embodiments of the present disclosure. FIG. 9 illustrates I-V curves of memory devices in accordance with some embodiments of the present disclosure. FIGS. 10A and 10B illustrate I-V curves and retention properties of memory devices in accordance with some embodiments of the present disclosure. FIG. 11 illustrates experiment results of memory devices in accordance with some embodiments of the present disclosure. FIG. 12A illustrates experiment results of memory devices in accordance with some embodiments of the present disclosure. FIG. 12B illustrates schematic views of resistive random access memory (RRAM) elements in accordance with some embodiments of the present disclosure. FIGS. 13A to 13F illustrate experiment results of memory devices in accordance with some embodiments of the present disclosure. FIG. 14 illustrates experiment results of memory devices in accordance with some embodiments of the present disclosure. FIGS. 15A to 15H illustrate a method for forming a resistive element in accordance to some embodiments of the present disclosure. FIGS. 16 to 31 illustrate a method in various stages of fabricating a memory device in accordance with some embodiments of the present disclosure. FIGS. 32 to 41 illustrate a method in various stages of fabricating a memory device in accordance with some embodiments of the present disclosure. FIGS. 42 to 53 illustrate a method in various stages of fabricating a memory device in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples.