US-20260129872-A1 - MEMORY SYSTEM

US20260129872A1US 20260129872 A1US20260129872 A1US 20260129872A1US-20260129872-A1

Abstract

A memory system comprises a substrate having a first substrate side and a second substrate side; and a memory media including a first memory stack mounted over the substrate. The substrate includes first signal substrate pads. The first signal substrate pads are closer to the first substrate side. The first memory stack includes a first memory chip and a second memory chip. The first memory chip includes first outer chip pads and first inner chip pads disposed adjacent to a first chip side. The second memory chip includes second outer chip pads and second inner chip pads disposed adjacent to a first chip side of the second memory chip. The corresponding first signal substrate pads, the corresponding first inner chip pads, and the corresponding second inner chip pads are electrically connected to each other.

Inventors

Seong Ju Lee

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (18)

1 . A memory system, comprising: a substrate having a first substrate side and a second substrate side, that is opposite to the first substrate side; and a memory media including a first memory stack mounted over the substrate, wherein: the substrate includes first signal substrate pads disposed over a surface of the substrate, wherein the first signal substrate pads are closer to the first substrate side than the second substrate side, the first memory stack includes a first memory chip and a second memory chip that is offset-stacked over the first memory chip, the first memory chip includes first outer chip pads and first inner chip pads, wherein the first outer chip pads and first inner chip pads are disposed adjacent to a first chip side of the first memory chip, wherein the first chip side of the first memory chip is closer to the first substrate side than the second substrate side, the first outer chip pads are disposed closer to the first chip side of the first memory chip than the first inner chip pads, the second memory chip includes second outer chip pads and second inner chip pads, wherein the second outer chip pads and the second inner chip pads are disposed adjacent to a first chip side of the second memory chip, wherein the first chip side of the second memory chip is closer to the first substrate side than the second substrate side, and the second outer chip pads are disposed closer to the first chip side of the second memory chip than the second inner chip pads, and the corresponding first signal substrate pads, the corresponding first inner chip pads, and the corresponding second inner chip pads are electrically connected to each other.
2 . The memory system of claim 1 , wherein the first outer chip pads and the second outer chip pads are floating.
3 . The memory system of claim 1 , wherein the first memory stack includes: a third memory chip that is offset-stacked over the second memory chip; and a fourth memory chip that is offset-stacked over the third memory chip, and wherein the third memory chip includes third outer chip pads and third inner chip pads, wherein the third outer chip pads and the third inner chip pads are disposed adjacent to a first chip side of the third memory chip closer to the first substrate side than the second substrate side, wherein the third outer chip pads are disposed closer to the first chip side of the third memory chip than the third inner chip pads, wherein the fourth memory chip includes fourth outer chip pads and fourth inner chip pads, wherein the fourth outer chip pads and the fourth inner chip pads are disposed adjacent to a first chip side of the fourth memory chip adjacent to the first substrate side, wherein the fourth outer chip pads are disposed closer to the first chip side of the fourth memory chip than the fourth inner chip pads, wherein the corresponding signal substrate pads, the corresponding first inner chip pads, the corresponding second inner chip pads, the corresponding third inner chip pads, and the corresponding fourth inner chip pads are electrically connected.
4 . The memory system of claim 3 , wherein the third outer chip pads and the fourth outer chip pads are floating.
5 . The memory system of claim 3 , wherein the substrate further includes first to fourth power substrate pads disposed on the surface of the substrate adjacent to the second substrate side, wherein the first memory chip further includes first power chip pads that are disposed adjacent to a second chip side of the first memory chip, which is opposite to the first chip side of the first memory chip, wherein the second memory chip further includes second power chip pads that are disposed adjacent to a second chip side of the second memory chip, which is opposite to the first chip side of the second memory chip, wherein the third memory chip further includes third power chip pads that are disposed adjacent to a second chip side of the third memory chip, which is opposite to the first chip side of the third memory chip, wherein the fourth memory chip further includes fourth power chip pads that are disposed adjacent to a second chip side of the fourth memory chip, which is opposite to the first chip side of the fourth memory chip, wherein the first power substrate pads are electrically connected to the first power chip pads, wherein the second power substrate pads are electrically connected to the second power chip pads, wherein the third power substrate pads are electrically connected to the third power chip pads, and wherein the fourth power substrate pads are electrically connected to the fourth power chip pads.
6 . The memory system of claim 1 , further comprising: a memory controller; an interface circuit; first parallel data channels between the memory controller and the interface circuit; and second parallel data channels between the interface circuit and the memory media.
7 . The memory system of claim 6 , wherein the first parallel data channels include DDR PHY interface (DFI) channels, and wherein the second parallel data channels include global input/output (GIO) channels.
8 . The memory system of claim 6 , wherein the memory media further includes a second memory stack mounted over the substrate, wherein the substrate includes second signal substrate pads exposed on the surface of the substrate adjacent to the first substrate side, and wherein the second signal substrate pads are electrically connected to the second memory stack.
9 . The memory system of claim 8 , wherein the substrate further includes first signal substrate interconnections and second signal substrate interconnections, wherein the first signal substrate interconnections are electrically connected to the corresponding first signal substrate pads, wherein the second signal substrate interconnections are electrically connected to the corresponding second signal substrate pads, wherein the second parallel data channels include a first set of second parallel data channels and a second set of second parallel data channels, wherein the first signal substrate interconnections are electrically connected to the first set of the second parallel data channels, and wherein the second signal substrate interconnections are electrically connected to the second set of the second parallel data channels.
10 . The memory system of claim 9 , wherein a number of the first parallel data channels is equal to a sum of a number of the second parallel data channels in the first set of the second parallel data channels and a number of the second parallel data channels in the second set of the second parallel data channels.
11 . A memory system, comprising: a memory controller; an interface circuit; DDR PHY Interface (DFI) channels between the memory controller and the interface circuit; a memory media; and global input/output (GIO) channels between the interface circuit and the memory media, wherein the memory media includes a first memory stack and a second memory stack that are mounted over a substrate, wherein each of the first memory stack and the second memory stack includes a first memory chip and a second memory chip that are offset-stacked over the substrate, wherein the substrate includes: first signal substrate interconnections and second signal substrate interconnections electrically connected to the GIO channels, respectively; first signal substrate pads electrically connected to the first signal substrate interconnections; and second signal substrate pads electrically connected to the second signal substrate interconnections, and wherein each of the first and second memory chips includes: outer chip pads and inner chip pads that are disposed adjacent to a first chip side of each of the first and second memory chips, wherein the outer chip pads are closer to the first chip side of each of the first and second memory chips than the inner chip pads, wherein the first signal substrate pads are electrically connected to the inner chip pads of the first and second memory chips of the first memory stack, and wherein the second signal substrate pads are electrically connected to the inner chip pads of the first and second memory chips of the second memory stack.
12 . The memory system of claim 11 , wherein each of the DFI channels and the GIO channels includes a plurality of data channels that are coupled in parallel.
13 . The memory system of claim 11 , wherein a number of the DFI channels and a number of the GIO channels are the same.
14 . The memory system of claim 13 , wherein the GIO channels include: a first set of the GIO channels electrically connected to the first memory stack, and a second set of the GIO channels electrically connected to the second memory stack.
15 . The memory system of claim 11 , wherein the outer chip pads of each of the first and second memory chips are floating.
16 . The memory system of claim 11 , wherein the substrate further includes power substrate pads, wherein the first and second memory chips further include power chip pads that are disposed adjacent to a second chip side of each of the first and second memory chips, wherein the second chip side is opposite to the first chip side, and wherein the power substrate pads are electrically connected to the power chip pads.
17 . The memory system of claim 11 , wherein the first memory chip includes: a first lower memory chip; a first intermediate memory chip that is offset-stacked over the first lower memory chip; and a first upper memory chip that is offset-stacked over the first intermediate memory chip, wherein the outer chip pads include: first lower outer chip pads that are disposed adjacent to a first chip side of the first lower memory chip; first intermediate outer chip pads that are disposed adjacent to a first chip side of the first intermediate memory chip; and first upper outer chip pads that are disposed adjacent to a first chip side of the first upper memory chip, wherein the inner chip pads include: first lower inner chip pads that are disposed adjacent to the first lower outer chip pads, wherein the first lower outer chip pads are closer to the first chip side of the first lower memory chip than the first lower inner chip pads; first intermediate inner chip pads that are disposed adjacent to the first intermediate outer chip pads, wherein the first intermediate outer chip pads are closer to the first chip side of the first intermediate memory chip than the first intermediate inner chip pads; and first upper inner chip pads that are disposed adjacent to the first upper outer chip pads, wherein the first upper outer chip pads are closer to the first chip side of the first upper memory chip than the first upper inner chip pads, wherein the corresponding first signal substrate pads, the corresponding first lower inner chip pads, the corresponding first intermediate inner chip pads, and the corresponding first upper inner chip pads are electrically connected.
18 . The memory system of claim 17 , wherein the second memory chip includes: a second lower memory chip; a second intermediate memory chip, which is offset-stacked over the second lower memory chip; and a second upper memory chip, which is offset-stacked over the second intermediate memory chip, wherein the outer chip pads include: second lower outer chip pads that are disposed adjacent to a first chip side of the second lower memory chip; second intermediate outer chip pads that are disposed adjacent to a first chip side of the second intermediate memory chip; and second upper outer chip pads that are disposed adjacent to a first chip side of the second upper memory chip, wherein the inner chip pads include: second lower inner chip pads that are disposed adjacent to the second lower outer chip pads, wherein the second lower outer chip pads are closer to the first chip side of the second lower memory chip than the second lower inner chip pads; second intermediate inner chip pads that are disposed adjacent to the second intermediate outer chip pads, wherein the second intermediate outer chip pads are closer to the first chip side of the second intermediate memory chip than the second intermediate inner chip pads; and second upper inner chip pads that are disposed adjacent to the second upper outer chip pads, wherein the second upper outer chip pads are closer to the first chip side of the second upper memory chip than the second upper inner chip pads, wherein the corresponding second signal substrate pads, the corresponding second lower inner chip pads, the corresponding second intermediate inner chip pads, and the corresponding second upper inner chip pads are electrically connected.

Description

BACKGROUND 1. Field Embodiments of the present disclosure relate to a memory system including a controller and a memory stack. 2. Description of the Related Art Various memory systems for high-speed operations and low power consumption are being studied. SUMMARY An embodiment of the present disclosure provides a memory system including a controller and a memory stack. An embodiment of the present disclosure provides a memory system in which a controller and a memory chip directly communicate with each other through channels that are arranged in parallel without a SERDES (serializer/de-serializer). An embodiment of the present disclosure provides a memory system having a memory stack in which all stacked memory chips operate in a slave mode. An embodiment of the present disclosure provides a method for operating a memory chip that functions as a master chip in a slave mode. In accordance with an embodiment of the present disclosure, a memory system comprises a substrate having a first substrate side and a second substrate side, that is opposite to the first substrate side; and a memory media including a first memory stack mounted over the substrate. The substrate includes first signal substrate pads disposed over a surface of the substrate. The first signal substrate pads are closer to the first substrate side than the second substrate side. The first memory stack includes a first memory chip and a second memory chip that is offset-stacked over the first memory chip. The first memory chip includes first outer chip pads and first inner chip pads. The first outer chip pads and first inner chip pads are disposed adjacent to a first chip side of the first memory chip. The first chip side of the first memory chip is closer to the first substrate side than the second substrate side. The first outer chip pads are disposed closer to the first chip side of the first memory chip than the first inner chip pads. The second memory chip includes second outer chip pads and second inner chip pads. The second outer chip pads and the second inner chip pads are disposed adjacent to a first chip side of the second memory chip. The first chip side of the second memory chip is closer to the first substrate side than the second substrate side. The second outer chip pads are disposed closer to the first chip side of the second memory chip than the second inner chip pads. The corresponding first signal substrate pads, the corresponding first inner chip pads, and the corresponding second inner chip pads are electrically connected to each other. In accordance with another embodiment of the present disclosure, a memory system comprises a memory controller; an interface circuit; DDR PHY Interface (DFI) channels between the memory controller and the interface circuit; a memory media; and global input/output (GIO) channels between the interface circuit and the memory media. The memory media includes a first memory stack and a second memory stack that are mounted over a substrate. Each of the first memory stack and the second memory stack includes a first memory chip and a second memory chip that are offset-stacked over the substrate. The substrate includes first signal substrate interconnections and second signal substrate interconnections electrically connected to the global input/output channels, respectively; first signal substrate pads electrically connected to the first signal substrate interconnections; and second signal substrate pads electrically connected to the second signal substrate interconnections. Each of the first and second memory chips includes outer chip pads and inner chip pads that are disposed adjacent to a first chip side of each of the first and second memory chips. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram schematically illustrating an electronic system in accordance with an embodiment of the present disclosure. FIG. 2 is a block diagram schematically illustrating a Compute eXpress Link (CXL) controller in accordance with an embodiment of the present disclosure. FIG. 3 is a block diagram schematically illustrating a memory media in accordance with an embodiment of the present disclosure. FIG. 4 is a block diagram schematically illustrating data channels for data communication in a memory system in accordance with an embodiment of the present disclosure. FIGS. 5A and 5B are top and side views schematically illustrating one memory stack in accordance with an embodiment of the present disclosure. FIG. 6 is a circuit diagram schematically illustrating a memory system in accordance with an embodiment of the present disclosure. FIG. 7 illustrates a memory chip operating in a slave mode in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION Embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodim