US-20260129873-A1 - SEMICONDUCTOR DEVICE

US20260129873A1US 20260129873 A1US20260129873 A1US 20260129873A1US-20260129873-A1

Abstract

A semiconductor device is disclosed. The semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate, each of the semiconductor chips having a first side surface, and a first conductive film, which is electrically connected to the package substrate and is extended to a region on the first side surfaces of the semiconductor chips. Each of the semiconductor chips may include a peripheral circuit structure including first bonding pads on a first surface of a substrate, a first cell array structure including a first stack and second bonding pads bonded to the first bonding pads, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film.

Inventors

Eunhye LEE
Keunyoung Lee
In-jae Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250521
Priority Date: 20241106

Claims (20)

1 . A semiconductor device, comprising: a package substrate; a plurality of semiconductor chips stacked on the package substrate, each of the semiconductor chips having a first side surface; and a first conductive film, which is electrically connected to the package substrate and is extended to a region on the first side surfaces of the semiconductor chips, wherein each of the semiconductor chips comprises: a peripheral circuit structure including first bonding pads on a first surface of a substrate; a first cell array structure including a first stack and second bonding pads bonded to the first bonding pads; and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film.
2 . The semiconductor device of claim 1 , wherein each of the semiconductor chips further comprises a conductive contact between the first and second bonding pads and the first input/output pad, and wherein the first input/output pad is electrically connected to the conductive contact and the first and second bonding pads.
3 . The semiconductor device of claim 2 , wherein the conductive contact is in contact with side surfaces of the first and second bonding pads.
4 . The semiconductor device of claim 1 , wherein the peripheral circuit structure comprises a peripheral interlayer insulating layer enclosing the first bonding pads, wherein the first cell array structure comprises an interlayer insulating layer enclosing the second bonding pads, and wherein the first input/output pad is disposed on side surfaces of the peripheral interlayer insulating layer and the interlayer insulating layer.
5 . The semiconductor device of claim 1 , wherein the first side surfaces of the semiconductor chips are aligned to each other.
6 . The semiconductor device of claim 1 , wherein each of the semiconductor chips further comprises second input/output pads, which are disposed on second side surfaces thereof.
7 . The semiconductor device of claim 6 , wherein the first side surface is opposite to the second side surface.
8 . The semiconductor device of claim 1 , wherein each of the semiconductor chips further comprises: vertical structures penetrating the first stack; and bit lines, which are disposed between the second bonding pads and the first stack in a vertical section and are connected to the vertical structures.
9 . A semiconductor device, comprising: a package substrate; a plurality of semiconductor chips stacked on the package substrate, each of the semiconductor chips having a first side surface; a mold layer provided on the package substrate to enclose the semiconductor chips; and a first conductive film electrically connected to the package substrate and extended to a region on the first side surfaces of the semiconductor chips, wherein each of the semiconductor chips comprises: a peripheral circuit structure including first bonding pads on a first surface of a substrate and second bonding pads on a second surface opposite to the first surface; a first cell array structure including third bonding pads bonded to the first bonding pads; and a first input/output pad, which is disposed on the first side surface and is electrically connected to the first conductive film, wherein the first cell array structure comprises: a first stack including first insulating patterns and first gate patterns, which are vertically and alternately stacked; vertical structures penetrating the first stack; and bit lines electrically connected to the vertical structures.
10 . The semiconductor device of claim 9 , wherein the peripheral circuit structure comprises a peripheral interlayer insulating layer enclosing the first bonding pads, wherein the first cell array structure comprises an interlayer insulating layer enclosing the third bonding pads, and wherein the first input/output pad is disposed on side surfaces of the peripheral interlayer insulating layer and the interlayer insulating layer.
11 . The semiconductor device of claim 9 , further comprising: a second conductive film electrically connected to interconnection patterns and extended to a region on second side surfaces of the semiconductor chips, wherein each of the semiconductor chips further comprises: a second cell array structure including fourth bonding pads, which are bonded to the second bonding pads; and a second input/output pad disposed on each of the second side surfaces and electrically connected to the second conductive film.
12 . The semiconductor device of claim 11 , wherein the first side surfaces of the semiconductor chips are aligned to each other, and wherein the second side surfaces of the semiconductor chips are aligned to each other.
13 . The semiconductor device of claim 11 , wherein the first input/output pad is electrically connected to one of the third bonding pads adjacent to the first side surface, and wherein the second input/output pad is electrically connected to one of the fourth bonding pads adjacent to the second side surface.
14 . The semiconductor device of claim 11 , wherein the first side surfaces are opposite to the second side surfaces.
15 . A semiconductor device, comprising: a peripheral circuit structure including first bonding pads on a first surface of a substrate and second bonding pads on a second surface of the substrate; and a first cell array structure opposite to the first surface; a second cell array structure opposite to the second surface; a first input/output pad on a first side surface of the peripheral circuit structure; and a second input/output pad on a second side surface of the peripheral circuit structure, wherein the first cell array structure comprises: a first stack including first insulating patterns and first gate patterns, which are vertically and alternately stacked; first vertical structures penetrating the first stack; and third bonding pads bonded to the first bonding pads, and wherein the second cell array structure comprises: a second stack including second insulating patterns and second gate patterns, which are vertically and alternately stacked; second vertical structures penetrating the second stack; and fourth bonding pads bonded to the second bonding pads.
16 . The semiconductor device of claim 15 , wherein the first cell array structure comprises first bit lines between the first vertical structures and the third bonding pads, when viewed in a vertical cross-section, and wherein the second cell array structure comprises second bit lines between the second vertical structures and the fourth bonding pads, when viewed in the vertical cross-section.
17 . The semiconductor device of claim 15 , wherein the first input/output pad is in contact with a first side surface of the first cell array structure, and wherein the second input/output pad is in contact with a second side surface of the second cell array structure.
18 . The semiconductor device of claim 17 , wherein the first input/output pad is electrically connected to one of the third bonding pads adjacent to the first side surface, and wherein the second input/output pad is electrically connected to one of the fourth bonding pads adjacent to the second side surface.
19 . The semiconductor device of claim 15 , wherein the peripheral circuit structure further comprises: a first peripheral interlayer insulating layer enclosing the first bonding pads; and a second peripheral interlayer insulating layer enclosing the second bonding pads, wherein the first cell array structure further comprises a first interlayer insulating layer enclosing the third bonding pads, wherein the second cell array structure further comprises a second interlayer insulating layer enclosing the fourth bonding pads, wherein the first input/output pad is placed on side surfaces of the first peripheral interlayer insulating layer and the first interlayer insulating layer, and wherein the second input/output pad is placed on side surfaces of the second peripheral interlayer insulating layer and the second interlayer insulating layer.
20 . The semiconductor device of claim 15 , wherein the peripheral circuit structure further comprises: peripheral circuits on the first surface of the substrate; and a penetration via pattern, which is provided to penetrate the substrate and is electrically connected to a portion of the peripheral circuits.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0156389, filed on Nov. 6, 2024, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION The present disclosure relates to a semiconductor device and a semiconductor package including the same. A semiconductor device capable of storing a large amount of data is required as a data storage of an electronic system. Accordingly, many studies are being conducted to increase the data storage capacity of the semiconductor device. For example, semiconductor devices, in which memory cells are three-dimensionally arranged, are being suggested. Furthermore, a semiconductor packaging technology of integrating a semiconductor device including memory cells in a single package is required. In the case of a semiconductor package in which multiple devices are integrated, there is a need to reduce the size of the semiconductor package and improve the heat-emission and electrical characteristics of the semiconductor package. SUMMARY An embodiment of the inventive concept provides a semiconductor device with an increased integration density. According to an embodiment of the inventive concept, a semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate, each of the semiconductor chips having a first side surface, and a first conductive film, which is electrically connected to the package substrate and is extended to a region on the first side surfaces of the semiconductor chips. Each of the semiconductor chips may include a peripheral circuit structure including first bonding pads on a first surface of a substrate, a first cell array structure including a first stack and second bonding pads bonded to the first bonding pads, and a first input/output pad disposed on the first side surface and electrically connected to the first conductive film. According to an embodiment of the inventive concept, a semiconductor device may include a package substrate, a plurality of semiconductor chips stacked on the package substrate, each of the semiconductor chips having a first side surface, a mold layer provided on the package substrate to enclose the semiconductor chips, and a first conductive film electrically connected to the package substrate and extended to a region on the first side surfaces of the semiconductor chips. Each of the semiconductor chips may include a peripheral circuit structure including first bonding pads on a first surface of a substrate and second bonding pads on a second surface opposite to the first surface, a first cell array structure including third bonding pads bonded to the first bonding pads, and a first input/output pad, which is disposed on the first side surface and is electrically connected to the first conductive film. The first cell array structure may include a first stack including first insulating patterns and first gate patterns, which are vertically and alternately stacked, vertical structures penetrating the first stack, and bit lines electrically connected to the vertical structures. According to an embodiment of the inventive concept, a semiconductor device may include a peripheral circuit structure including first bonding pads on a first surface of a substrate and second bonding pads on a second surface of the substrate, and a first cell array structure opposite to the first surface, a second cell array structure opposite to the second surface, a first input/output pad on a first side surface of the peripheral circuit structure, and a second input/output pad on a second side surface of the peripheral circuit structure. The first cell array structure may include a first stack including first insulating patterns and first gate patterns, which are vertically and alternately stacked, first vertical structures penetrating the first stack, and third bonding pads bonded to the first bonding pads. The second cell array structure may include a second stack including second insulating patterns and second gate patterns, which are vertically and alternately stacked, second vertical structures penetrating the second stack, and fourth bonding pads bonded to the second bonding pads. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram schematically illustrating an electronic system including a semiconductor device according to an example embodiment of the inventive concept. FIG. 2A is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept. FIG. 2B is a sectional view taken along a line A-A′ of FIG. 2A to illustrate a semiconductor device according to an example embodiment of the inventive concept. FIG. 3A is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept. FIG. 3B is a sectional view taken alo