US-20260129875-A1 - SEMICONDUCTOR PACKAGE

US20260129875A1US 20260129875 A1US20260129875 A1US 20260129875A1US-20260129875-A1

Abstract

A semiconductor package includes a buffer die, a core die stack on the buffer die, the core die stack including a plurality of core dies stacked in a vertical direction perpendicular to an upper surface of the buffer die, and including a first sidewall, and an adhesive film including a first portion and a second portion, wherein the first portion of the adhesive film is arranged on a lower surface of a top die, the top die being disposed at an uppermost portion of the core die stack, the second portion of the adhesive film extends in a vertical direction and contacts the first sidewall of the core die stack, and the second portion of the adhesive film contacts an upper surface of the buffer die.

Inventors

Hyeonkyu HA

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250701
Priority Date: 20241107

Claims (20)

1 . A semiconductor package comprising: a buffer die; a core die stack on the buffer die, the core die stack comprising a plurality of core dies stacked in a vertical direction perpendicular to an upper surface of the buffer die, and including a first sidewall; and an adhesive film including a first portion and a second portion, wherein the first portion of the adhesive film is arranged on a lower surface of a top die, the top die being disposed at an uppermost portion of the core die stack, the second portion of the adhesive film extends in a vertical direction and contacts the first sidewall of the core die stack, and the second portion of the adhesive film contacts an upper surface of the buffer die.
2 . The semiconductor package of claim 1 , wherein the adhesive film comprises a non-conductive film (NCF).
3 . The semiconductor package of claim 1 , wherein the adhesive film is formed of a polymer material.
4 . The semiconductor package of claim 1 , wherein the top die comprises a dummy die.
5 . The semiconductor package of claim 1 , wherein the second portion of the adhesive film covers all sidewalls of the core dies positioned between the upper surface of the buffer die and the top die.
6 . The semiconductor package of claim 1 , wherein a thermal compression bond is formed between the top die and a core die, including in the plurality of core dies, disposed directly below the top die.
7 . The semiconductor package of claim 1 , wherein each of the plurality of core dies comprises a semiconductor substrate, an internal circuit region disposed under the semiconductor substrate, and a back protective layer disposed on the semiconductor substrate, and further comprises a through electrode structure that extends through the back protective layer and the semiconductor substrate into the internal circuit region.
8 . The semiconductor package of claim 7 , wherein each of the plurality of core dies comprises a lower bonding pad and a lower bonding insulating layer disposed under a front surface of the semiconductor substrate, and an upper bonding pad and an upper bonding insulating layer disposed over a back surface of the semiconductor substrate.
9 . The semiconductor package of claim 8 , wherein, between each directly adjacent pairs of the plurality of core dies stacked in the vertical direction, an upper bonding pad of a lower core die included in a respective adjacent pair of the plurality of core dies is in contact with and bonded to a lower bonding pad of an upper core die include in the respective adjacent pair of the plurality of core dies, and the upper bonding insulating layer of the lower core die is in contact with and bonded to the lower bonding insulating layer of the upper core die.
10 . The semiconductor package of claim 1 , further comprising a molding layer that, with respect to a top down view, surrounds the core die stack and the adhesive film, wherein the adhesive film is formed of a first material, and the molding layer is formed of a second material that is different from the first material.
11 . The semiconductor package of claim 1 , wherein directly adjacent pairs of the plurality of core dies disposed below the top die in in the vertical direction are bonded together with hybrid bonding such that portions of their respective facing surfaces are merged together, and wherein the top die is bonded to the core die, included in the plurality of core dies, that is directly below the top die in the vertical direction using the adhesive film.
12 . The semiconductor package of claim 1 , wherein a horizontal cross-sectional area of the buffer die is greater than a horizontal cross-sectional area of the core die stack.
13 . A semiconductor package comprising: a buffer die; a core die stack on the buffer die, the core die stack comprising first dies stacked in a vertical direction perpendicular to an upper surface of the buffer die to form a stacked structure, and a second die disposed on the stacked structure; a horizontal portion of an adhesive film, which bonds a top first die, positioned at an uppermost portion of the stacked structure among the first dies, to the second die; a fillet portion of the adhesive film, the fillet portion extends along a sidewall of the core die stack toward the upper surface of the buffer die, wherein a first end of the fillet portion is integrally connected to the horizontal portion of the adhesive film, and a second end of the fillet portion, opposite to the first end, is in contact with the upper surface of the buffer die; and a molding layer that covers a top surface of the buffer die and surrounds the core die stack, the horizontal portion of the adhesive film, and the fillet portion of the adhesive film, wherein the first dies are hybrid bonded to each other.
14 . The semiconductor package of claim 13 , wherein the horizontal portion of the adhesive film and the fillet portion of the adhesive film comprise a non-conductive film (NCF).
15 . The semiconductor package of claim 13 , wherein the horizontal portion of the adhesive film and the fillet portion of the adhesive film is formed of a polymer.
16 . The semiconductor package of claim 13 , wherein bonding between the top first die and the second die is by a thermal compression process using the horizontal portion of the adhesive film as a medium.
17 . The semiconductor package of claim 13 , wherein a lowermost first die positioned at a lowermost portion among the first dies, the buffer die, and the second end of the fillet portion of the adhesive film are connected to each other.
18 . The semiconductor package of claim 13 , wherein each of the first dies comprises a semiconductor substrate, an internal circuit region disposed under the semiconductor substrate, and a back protective layer disposed on the semiconductor substrate, and further comprises a through electrode structure that extends through the back protective layer and the semiconductor substrate into the internal circuit region.
19 . The semiconductor package of claim 13 , wherein a horizontal cross-sectional area of the buffer die is greater than a horizontal cross-sectional area of the core die stack.
20 . A semiconductor package comprising: a buffer die; core dies disposed on the buffer die and hybrid bonded to each other; a dummy die arranged on the core dies; an adhesive film between the core dies and the dummy die; a fillet connected to an end of the adhesive film and that extends vertically downward along sidewalls of the core dies and contacts the buffer die; and a molding layer that covers a top surface of the buffer die and surrounds the core dies, the dummy die, the adhesive film, and the fillet, wherein the dummy die is bonded to the core dies by a thermal compression process, the fillet is a portion of the adhesive film, which has melted and is hardened through the thermal compression process, each of the core dies comprises a semiconductor substrate, an internal circuit region disposed under the semiconductor substrate, a back protective layer disposed on the semiconductor substrate, and a through electrode structure that extends through the back protective layer and the semiconductor substrate into the internal circuit region, and a core die positioned at a lowermost portion among the core dies, the buffer die, and the fillet are connected to each other.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0156886, filed on Nov. 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Aspects of the inventive concept relate to a semiconductor package. More specifically, aspects of the inventive concept relate to a semiconductor package manufactured through a thermal compression process using a non-conductive film (NCF). Over the past several decades, advances in technology, materials, and manufacturing processes have led to rapid advances in computing power and wireless communications technology. This has enabled implementation of high-integration and high-performance transistors, and the speed of integration has doubled approximately every 18 months according to Moore's law. Miniaturization and power efficiency of systems are the ongoing goals of semiconductor manufacturing, and at this point, when the economic and physical process limits are being reached, 3D integrated packaging is presented as an effective solution. SUMMARY Aspects of the inventive concept provide a semiconductor package with improved reliability and performance. The objective to be solved by the application is not limited to the objectives above, and other objectives will be clearly understood by those skilled in the art from the description below. In order to achieve the technical problem, aspects of the inventive concept provide a semiconductor package as below. According to an aspect of the inventive concept, there is provided a semiconductor package including a buffer die, a core die stack on the buffer die, the core die stack including a plurality of core dies stacked in a vertical direction perpendicular to an upper surface of the buffer die, and including a first sidewall, and an adhesive film including a first portion and a second portion, wherein the first portion of the adhesive film is arranged on a lower surface of a top die, the top die being disposed at an uppermost portion of the core die stack, the second portion of the adhesive film extends in a vertical direction and contacts the first sidewall of the core die stack, and the second portion of the adhesive film contacts an upper surface of the buffer die. According to another aspect of the inventive concept, there is provided a semiconductor package including a buffer die, a core die stack on the buffer die, the core die stack including first dies stacked in a vertical direction perpendicular to an upper surface of the buffer die to form a stacked structure, and a second die disposed on the stacked structure, a horizontal portion of an adhesive film, which bonds a top first die, positioned at an uppermost portion of the stacked structure among the first dies, to the second die, a fillet portion of the adhesive film, the fillet portion extends along the sidewall of the core die stack toward the upper surface of the buffer die, wherein a first end of the fillet portion is integrally connected to the horizontal portion of the adhesive film, and a second end of the fillet portion, opposite to the first end, is in contact with the upper surface of the buffer die, and a molding layer that covers a top surface of the buffer die and surrounds the core die stack, the horizontal portion of the adhesive film, and the fillet portion of the adhesive film, wherein all bonding between the first dies is by a direct bonding process. According to another aspect of the inventive concept, there is provided a semiconductor package including a buffer die, core dies disposed on the buffer die and hybrid bonded to each other, a dummy die arranged on the core dies, an adhesive film between the core dies and the dummy die, a fillet connected to an end of the adhesive film and that extends vertically downward along sidewalls of the core and contacts the buffer die, and a molding layer that covers a top surface of the buffer die and surrounds the core dies, the dummy die, the adhesive film, and the fillet, wherein the dummy die is bonded to the core dies by a thermal compression process, the fillet is a portion of the adhesive film, which has melted and is hardened through the thermal compression process, each of the core dies includes a semiconductor substrate, an internal circuit region disposed under the semiconductor substrate, a back protective layer disposed on the semiconductor substrate, and a through electrode structure that extends through the back protective layer and the semiconductor substrate into the internal circuit region, and a core die positioned at a lowermost portion among the core dies, the buffer die, and the fillet are connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a layout diagr