US-20260129876-A1 - SEMICONDUCTOR DEVICE

US20260129876A1US 20260129876 A1US20260129876 A1US 20260129876A1US-20260129876-A1

Abstract

A semiconductor device includes a first semiconductor substrate including a first semiconductor device, a second semiconductor substrate including a second semiconductor device, and a bonding region that is between the first semiconductor device and the second semiconductor device and includes a first region, a second region, and a third region that is between the first region and the second region and extends around the first region, where the bonding region includes: a first bonding pad on the first region, a second bonding pad on the second region, and a third bonding pad on the third region, and where the third bonding pad extends around the first bonding pad.

Inventors

Jaeho Jeong
Bonghyun Choi

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250918
Priority Date: 20241101

Claims (20)

1 . A semiconductor device, comprising: a first semiconductor substrate comprising a first semiconductor device; a second semiconductor substrate comprising a second semiconductor device; and a bonding region that is between the first semiconductor device and the second semiconductor device and comprises a first region, a second region, and a third region that is between the first region and the second region and extends around the first region, wherein the bonding region comprises: a first bonding pad on the first region; a second bonding pad on the second region; and a third bonding pad on the third region, and wherein the third bonding pad extends around the first bonding pad.
2 . The semiconductor device of claim 1 , wherein the third region entirely extends around the first region in a first direction and a second direction that are parallel to an upper surface of the first semiconductor device.
3 . The semiconductor device of claim 2 , wherein the third bonding pad entirely extends around the first region in the first direction and the second direction and extends in a linear shape along the third region.
4 . The semiconductor device of claim 1 , wherein: the first bonding pad comprises a first bottom bonding pad on the first semiconductor device and a first top bonding pad that is on the second semiconductor device and is bonded to the first bottom bonding pad, the second bonding pad comprises a second bottom bonding pad on the first semiconductor device and a second top bonding pad that is on the second semiconductor device and is bonded to the second bottom bonding pad, and the third bonding pad comprises a third bottom bonding pad on the first semiconductor device and a third top bonding pad that is on the second semiconductor device and is bonded to the third bottom bonding pad.
5 . The semiconductor device of claim 1 , wherein the first bonding pad is electrically connected to at least one of the first semiconductor device or the second semiconductor device.
6 . The semiconductor device of claim 5 , wherein the second bonding pad is electrically insulated from the first semiconductor device and the second semiconductor device.
7 . The semiconductor device of claim 6 , wherein the third bonding pad is electrically insulated from the first semiconductor device and the second semiconductor device.
8 . The semiconductor device of claim 5 , wherein: at least a portion of the third bonding pad overlaps at least one of the first semiconductor device or the second semiconductor device in a first direction, and the first direction is parallel to an upper surface of the first semiconductor device.
9 . The semiconductor device of claim 1 , wherein the third bonding pad extends in a linear shape along the third region, and a width of the third bonding pad in a first direction that is parallel to an upper surface of the first semiconductor device is less than or equal to a width of the first bonding pad in the first direction.
10 . A semiconductor device, comprising: a substrate; a peripheral circuit structure on the substrate; a cell structure on the peripheral circuit structure; and a bonding region comprising a first bonding pad, a second bonding pad, and a third bonding pad between the peripheral circuit structure and the cell structure, wherein the first bonding pad is on a first region of the bonding region, wherein the second bonding pad is on a second region of the bonding region, wherein the third bonding pad is on a third region of the bonding region, wherein the third region is between the first region and the second region and extends around the first region, and wherein the third bonding pad extends around the first bonding pad.
11 . The semiconductor device of claim 10 , wherein the cell structure comprises: a mold structure comprising a plurality of gate electrodes and a mold insulating layer that extends around the plurality of gate electrodes; a plurality of channel structures that extend into the mold structure in a first direction; and a plurality of word line structures respectively contacting the plurality of gate electrodes, wherein the first direction is perpendicular to an upper surface of the substrate.
12 . The semiconductor device of claim 10 , wherein the third region entirely extends around the first region in a first direction and a second direction that are parallel to an upper surface of the substrate.
13 . The semiconductor device of claim 12 , wherein the third bonding pad extends in a linear shape along the third region and entirely extends around the first region in the first direction and the second direction.
14 . The semiconductor device of claim 10 , wherein the first bonding pad is electrically connected to at least one of the cell structure or the peripheral circuit structure.
15 . The semiconductor device of claim 14 , wherein the second bonding pad and the third bonding pad are electrically insulated from the cell structure and the peripheral circuit structure.
16 . The semiconductor device of claim 10 , wherein at least a portion of the third bonding pad overlaps at least one of the cell structure or the peripheral circuit structure in a first direction that is parallel to an upper surface of the substrate.
17 . The semiconductor device of claim 10 , wherein the third bonding pad extends in a linear shape along the third region, and a width of the third bonding pad in a first direction that is parallel to an upper surface of the substrate is less than or equal to a width of the first bonding pad in the first direction.
18 . The semiconductor device of claim 10 , further comprising a plurality of first bonding pads that comprises the first bonding pad, and wherein, in a first direction that is parallel to an upper surface of the substrate, a distance between the first bonding pad and the third bonding pad is greater than or equal to a distance between a second one of the plurality of first bonding pads and a third one of the plurality of first bonding pads.
19 . The semiconductor device of claim 10 , wherein the first bonding pad comprises a first bottom bonding pad and a first top bonding pad, and wherein the first bottom bonding pad overlaps a portion of the first top bonding pad in a first direction that is perpendicular to an upper surface of the substrate.
20 . A semiconductor device, comprising: a first semiconductor substrate comprising a first semiconductor device; a second semiconductor substrate comprising a second semiconductor device; and a bonding region that is between the first semiconductor device and the second semiconductor device and comprises a first region, a second region, and a third region between the first region and the second region and extending around the first region, and wherein the bonding region comprises: a first bonding pad on the first region, wherein the first bonding pad comprises a first bottom bonding pad on the first semiconductor device and a first top bonding pad on the second semiconductor device; a second bonding pad on the second region, wherein the second bonding pad comprises a second bottom bonding pad on the first semiconductor device and a second top bonding pad on the second semiconductor device; and a third bonding pad on the third region, wherein the third bonding pad comprises a third bottom bonding pad on the first semiconductor device and a third upper bonding pad on the second semiconductor device, wherein the third region entirely extends around the first region in a first direction and a second direction that are parallel to an upper surface of the first semiconductor device, and wherein the third bonding pad extends in a linear shape along the third region and entirely extends around the first region in the first direction and the second direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to Korean Patent Application No. 10-2024-0153182, filed on Nov. 1, 2024, the entire contents of which are incorporated herein for all purposes by this reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device. BACKGROUND A semiconductor device may be a component used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices may be manufactured. For example, a memory device may be used to store and retrieve data, and a non-memory device may be used to control or amplify electrical signals. A semiconductor device is a desirable element in electronic devices, and is desirable in various industries such as computers, communication equipment, consumer electronics, etc. A process of bonding two (2) or more wafers by using a hybrid bonding technique, etc. may be used to improve the integration of semiconductor devices. In the wafer bonding process, defects occur due to, for example, particles remaining between wafers. Therefore, measures for ensuring the reliability of semiconductor devices may be desired. SUMMARY The present disclosure aims to provide a semiconductor device with improved electrical characteristics and reliability. According to some embodiments of the present disclosure, a third bonding pad may be placed to surround or extends around a bonding pad disposed in a region that performs a target or predetermined electrical operation to prevent or inhibit the propagation of voids or cracks to the region during a subsequent heat treatment process, a dividing process, a reliability evaluation process, etc. Accordingly, the reliability of semiconductor devices may be improved by preventing or inhibiting the quality deterioration or the defect occurrence of the semiconductor devices. According to some embodiments of the present disclosure, the third bonding pad may be formed to have a closed shape (e.g., a closed curve shape) to prevent or inhibit the occurrence of unbonded portions or voids during the bonding process of the third bonding pad. Accordingly, the reliability of semiconductor devices may be improved. According to some embodiments of the present disclosure, a semiconductor device may include a first semiconductor substrate including a first semiconductor device, a second semiconductor substrate including a second semiconductor device, and a bonding region that is between the first semiconductor device and the second semiconductor device and includes a first region, a second region, and a third region that is between the first region and the second region and extends around the first region, where the bonding region includes: a first bonding pad on the first region, a second bonding pad on the second region, and a third bonding pad on the third region, and where the third bonding pad extends around the first bonding pad. According to some embodiments of the present disclosure, a semiconductor device may include a substrate, a peripheral circuit structure on the substrate, a cell structure on the peripheral circuit structure, and a bonding region including a first bonding pad, a second bonding pad, and a third bonding pad between the peripheral circuit structure and the cell structure, where the first bonding pad is on a first region of the bonding region, where the second bonding pad is on a second region of the bonding region, where the third bonding pad is on a third region of the bonding region, where the third region is between the first region and the second region and extends around the first region, and where the third bonding pad extends around the first bonding pad. According to some embodiments of the present disclosure, a semiconductor device may include a first semiconductor substrate including a first semiconductor device, a second semiconductor substrate including a second semiconductor device, and a bonding region that is between the first semiconductor device and the second semiconductor device and includes a first region, a second region, and a third region between the first region and the second region and extending around the first region, and where the bonding region includes: a first bonding pad on the first region, where the first bonding pad includes a first bottom bonding pad on the first semiconductor device and a first top bonding pad on the second semiconductor device, a second bonding pad on the second region, where the second bonding pad includes a second bottom bonding pad on the first semiconductor device and a second top bonding pad on the second semiconductor device, and a third bonding pad on the third region, where the third bonding pad includes a third bottom bonding pad on the first semiconductor device and a third upper bonding pad on the second semiconductor device, where the third region entirely extends around the first region in a first direction and a second direction that are parallel to an upper surfa