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US-20260129877-A1 - 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC CIRCUITS, MEMORY CELLS, AND PROCESSOR ARRAY

US20260129877A1US 20260129877 A1US20260129877 A1US 20260129877A1US-20260129877-A1

Abstract

An integrated semiconductor device including: a first level including single crystal silicon and logic circuits each include first transistors; a second level, disposed above the first level and includes arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; a plurality of SerDes circuits; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate having an area greater than 1,000 mm2, and where the substrate includes at least one interconnect.

Inventors

  • Zvi Or-Bach
  • Jin-Woo Han
  • Brian Cronquist

Assignees

  • MONOLITHIC 3D INC.

Dates

Publication Date
20260507
Application Date
20251118

Claims (20)

  1. 1 . An integrated semiconductor device, the device comprising: a first level; a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of first memory cells, wherein said second level comprises a plurality of second transistors, wherein each of said first memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level; an array of processors; a plurality of SerDes circuits; and a third level, wherein said third level comprises a plurality of third transistors, wherein said third level is disposed above said second level and comprises a plurality of arrays of second memory cells, wherein each of said second memory cells comprises at least one of said third transistors, wherein said device comprises a substrate having an area greater than 1,000 mm 2 , and wherein said substrate comprises at least one interconnect.
  2. 2 . The device according to claim 1 , wherein said third level comprises a plurality of RF circuits.
  3. 3 . The device according to claim 1 , further comprising: channels adapted for fluid cooling.
  4. 4 . The device according to claim 1 , wherein said substrate comprises single crystal silicon.
  5. 5 . The 3D device according to claim 1 , further comprising: a bonding structure, wherein said bonding structure comprises regions of oxide-to-oxide bonds, and wherein said bonding structure comprises regions of metal-to-metal bonds.
  6. 6 . The 3D device according to claim 1 , wherein said first memory cells comprise Dynamic Random Access Memory (“DRAM”) cells.
  7. 7 . The 3D device according to claim 1 , wherein said first level comprises a plurality of TSVs.
  8. 8 . An integrated semiconductor device, the device comprising: a first level; a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of first memory cells, wherein said second level comprises a plurality of second transistors, wherein each of said first memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level; an array of processors; a third level, wherein said third level comprises a plurality of third transistors, wherein said third level is disposed above said second level and comprises a plurality of arrays of second memory cells, wherein each of said second memory cells comprises at least one of said third transistors, wherein said first memory cells comprise Dynamic Random Access Memory (“DRAM”) cells, wherein said device comprises a substrate having an area greater than 1,000 mm 2 , and wherein said substrate comprises at least one interconnect; and a bonding structure, wherein said bonding structure comprises regions of metal-to-metal bonds.
  9. 9 . The device according to claim 8 , wherein said third level comprises a plurality of RF circuits.
  10. 10 . The device according to claim 8 , further comprising: channels adapted for fluid cooling.
  11. 11 . The device according to claim 8 , further comprising: a plurality of SerDes circuits.
  12. 12 . The 3D device according to claim 8 , wherein said device comprises a plurality of transmission lines.
  13. 13 . The 3D device according to claim 8 , wherein said substrate comprises single crystal silicon.
  14. 14 . The 3D device according to claim 8 , wherein said first level comprises a plurality of TSVs.
  15. 15 . An integrated semiconductor device, the device comprising: a first level; a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of first memory cells, wherein said second level comprises a plurality of second transistors, wherein each of said first memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level; a bonding structure, wherein said bonding structure comprises regions of metal-to-metal bonds; an array of processors; and a third level, wherein said third level comprises a plurality of third transistors, wherein said third level is disposed above said second level and comprises a plurality of arrays of second memory cells, wherein each of said second memory cells comprises at least one of said third transistors, wherein said first level comprises a plurality of TSVs, wherein said device comprises a substrate having an area greater than 1,000 mm 2 , and wherein said single crystal silicon substrate comprises at least one interconnect.
  16. 16 . The device according to claim 15 , wherein said third level comprises a plurality of RF circuits.
  17. 17 . The device according to claim 15 , further comprising: channels adapted for fluid cooling.
  18. 18 . The 3D device according to claim 1 , wherein said bonding structure comprises regions of oxide-to-oxide bonds.
  19. 19 . The 3D device according to claim 1 , wherein said first memory cells comprise Dynamic Random Access Memory (“DRAM”) cells.
  20. 20 . The 3D device according to claim 1 , wherein said substrate comprises single crystal silicon.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Memory Circuit (3D-Memory) and Three Dimensional Integrated Logic Circuit (3D-Logic) devices and fabrication methods. 2. Discussion of Background Art Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs. 3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low and wire. There are many techniques to construct 3D stacked integrated circuits or chips including: Through-silicon via (TSV) technology: Multiple layers of dice are constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,406,670, 9,460,978, 9,509,313, 9,640,531, 9,691,760, 9,711,407, 9,721,927, 9,799,761, 9,871,034, 9,953,870, 9,953,994, 10,014,292, 10,014,318, 10,515,981, 10,892,016, 10,991,675, 11,121,121, 11,502,095, 10,892,016, 11,270,988; and pending U.S. patent application Publications and applications, Ser. Nos. 14/642,724, 15/150,395, 15/173,686, 62/651,722; 62/681,249, 62/713,345, 62/770,751, 62/952,222, 62/824,288, 63/075,067, 63/091,307, 63/115,000, 63/220,443, 2021/0242189, 2020/0013791; and PCT Applications (and Publications): PCT/US2010/052093, PCT/US2011/042071 (WO2012/015550), PCT/US2016/52726 (WO2017053329), PCT/US2017/052359 (WO2018/071143), PCT/US2018/016759 (WO2018144957), PCT/US2018/52332(WO 2019/060798), PCT/US2021/44110, and PCT/US22/44165. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference.Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031, 9,941,319, 10,679,977, 10,943,934, 10,998,374, 11,063,071, and 11,133,344. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference. Additionally the 3D technology according to some embodiments of the invention may enable some very innovative IC devices alternatives with reduced development costs, novel and simpler process flows, increased yield, and other illustrative benefits. SUMMARY The invention relates to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods. Important aspects of 3D IC are technologies that allow layer transfer. These technologies include technologies that support reuse of the donor wafer, and technologies that support fabrication of active devices on the transferred layer to be transferred with it. In one aspect, a 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of arrays of memory cells, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2. In another aspect, a 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of RF circuits, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2. In another aspect, a 3D semicondu