US-20260129879-A1 - SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

US20260129879A1US 20260129879 A1US20260129879 A1US 20260129879A1US-20260129879-A1

Abstract

An image sensor device includes a capacitor structure that includes, as a dielectric material, an amorphous composition that includes a mixture of metal oxides. The amorphous composition replaces crystalline metal oxide dielectric layer stacks used in other approaches. The amorphous composition reduces or prevents interface defects and electron traps as compared to the crystalline metal oxide dielectric layer stacks. A single amorphous layer avoids the interfaces between metal oxides and metal oxide crystal defects in which the electron traps can be easily formed. The resulting image sensor device exhibits reduced lag as compared to other approaches that use crystalline metal oxide dielectric layer stacks. In addition, using the single amorphous layer including the mixture of metal oxides increases capacitance of a corresponding capacitor structure as compared to other approaches that use the crystalline metal oxide dielectric layer stacks.

Inventors

Min-Ying Tsai
Cheng-Hsien Chou
I Wen HUANG

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A method, comprising: forming a trench in a dielectric layer; depositing, in the trench, a first electrode layer of a semiconductor layer stack; depositing, in the trench, an insulator layer of the semiconductor layer stack on the first electrode layer; and depositing, in the trench, a second electrode layer of the semiconductor layer stack on the insulator layer, wherein the semiconductor layer stack extends along sidewalls and a bottom surface of the trench, and wherein the insulator layer is an amorphous layer comprising a combination of metals and oxygen.
2 . The method of claim 1 , wherein depositing the insulator layer comprises: performing a plurality of atomic layer deposition (ALD) cycles to deposit the insulator layer, wherein performing an ALD cycle, of the plurality of ALD cycles, comprises: depositing, using a first material precursor, zirconium oxide; and depositing, using a second material precursor, aluminum oxide on the zirconium oxide.
3 . The method of claim 2 , wherein performing the ALD cycle further comprises: oxidizing the first material precursor to form the zirconium oxide; and oxidizing the second material precursor to form the aluminum oxide.
4 . The method of claim 2 , wherein a deposited thickness of the zirconium oxide is greater than a deposited thickness of the aluminum oxide.
5 . The method of claim 2 , wherein a deposited thickness of the zirconium oxide is smaller than a deposited thickness of the aluminum oxide.
6 . The method of claim 2 , wherein a deposited thickness of the zirconium oxide is approximately equal to a deposited thickness of the aluminum oxide.
7 . The method of claim 2 , wherein the plurality of ALD cycles are performed to deposit alternating atomic layers of zirconium oxide and aluminum oxide.
8 . The method of claim 1 , further comprising performing a surface treatment operation on the first electrode layer to transform a portion of the first electrode layer into a buffer layer on the first electrode layer, wherein the surface treatment operation is performed prior to depositing the insulator layer and the insulator layer is deposited on the buffer layer.
9 . The method of claim 1 , wherein the insulator layer contains at least one of a tetragonal phase or a cubic phase.
10 . The method of claim 1 , wherein the metals comprise aluminum and zirconium, and wherein a ratio of a concentration of zirconium to a concentration of aluminum in the insulator layer is substantially uniform at different depths of the insulator layer.
11 . The method of claim 1 , wherein the metals comprise aluminum and zirconium, and wherein a concentration of zirconium in the insulator layer is greater than a concentration of aluminum in the insulator layer.
12 . A method, comprising: depositing a first conductive layer in a trench that was formed in a dielectric layer, wherein the first conductive layer extends along sidewalls and a bottom surface of the trench; performing a treatment operation to transform a portion of the first conductive layer into a buffer layer; depositing an insulator layer on the buffer layer, wherein the insulator layer is an amorphous composition that includes a mixture of a first metal material, a second metal material, and oxygen; and depositing a second conductive layer on the insulator layer.
13 . The method of claim 12 , wherein at least some of the first metal material and a first portion of the oxygen are bonded to each other in a first high dielectric constant (high-k) metal oxide, and at least some of the second metal material and a second portion of the oxygen are bonded to each other in a second high-k metal oxide.
14 . The method of claim 13 , wherein depositing the insulator layer comprises: performing a plurality of atomic layer deposition (ALD) cycles to deposit alternating layers of the first high-k metal oxide and the second high-k metal oxide.
15 . The method of claim 14 , wherein atomic layers of the first high-k metal oxide are deposited at a greater rate than atomic layers of the second high-k metal oxide.
16 . The method of claim 14 , wherein the insulator layer is deposited such that a ratio of the first high-k metal oxide to the second high-k metal oxide is included in a range of approximately 3:4 to approximately 9:2.
17 . A capacitor structure, comprising: a first electrode layer that extends along sidewalls and a bottom surface of a trench; a second electrode layer in the trench; and an insulator layer between the first electrode layer and the second electrode layer, wherein the insulator layer extends along the sidewalls and the bottom surface of the trench, and wherein the insulator layer has a non-crystalline structure that contains a mixture of a plurality of high dielectric constant (high-k) dielectric oxide materials.
18 . The capacitor structure of claim 17 , wherein a first high-k dielectric oxide material of the plurality of high-k dielectric oxide materials comprises zirconium oxide, and a second high-k dielectric oxide material of the plurality of high-k dielectric oxide materials comprises aluminum oxide.
19 . The capacitor structure of claim 17 , wherein the plurality of high-k dielectric oxide materials have different concentrations from each other in the insulator layer.
20 . The capacitor structure of claim 17 , wherein the insulator layer is a single amorphous layer.

Description

BACKGROUND A complementary metal oxide semiconductor (CMOS) image sensor may include a plurality of pixel sensors arranged in a pixel sensor array. A pixel sensor of the CMOS image sensor may include a photodiode configured to convert photons of incident light to a photocurrent of electrons. The magnitude of the photocurrent is based at least in part on the intensity of the incident light. Accordingly, if the pixel sensors in the pixel sensor array are capable of sensing incident light across a broad range of intensity, a high range of brightness and contrast may be achieved in images and/or video generated by the CMOS image sensor. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A and 1B are diagrams of example circuits for a pixel sensor described herein. FIGS. 2A and 2B are diagrams of an example semiconductor device described herein. FIGS. 3A-3E are diagrams of an example implementation of forming a semiconductor device described herein. FIGS. 4A-4Q are diagrams of an example implementation of forming a trench capacitor structure described herein. FIGS. 5A and 5B are diagrams of an example implementation of an insulator layer of a capacitor structure described herein. FIG. 6 illustrates an elemental composition of an insulator layer of a capacitor structure described herein. FIG. 7 is a diagram of an example semiconductor device described herein. FIG. 8 is a diagram of an example semiconductor device described herein. FIG. 9 is a diagram of an example semiconductor device described herein. FIG. 10 is a flowchart of an example process associated with forming a semiconductor device described herein. FIG. 11 is a flowchart of an example process associated with forming a semiconductor device described herein. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some cases, a pixel sensor may be limited in the number of photons of incident light that can be absorbed before reaching saturation of the pixel sensor. “Saturation” refers to a level of photon absorption past which additional photons of light cannot be absorbed by the pixel sensor. Saturation of the pixel sensor results in limited dynamic range for the pixel sensor because additional brightness and color information cannot be obtained from further absorption of photons. The amount of photocurrent charge that can be stored in a pixel sensor before reaching saturation may be referred to as the full well capacity (FWC) of the pixel sensor. The full well capacity of the pixel sensor may be based at least in part on the size (e.g., the depth, the width, the volume) of the photodiode of the pixel sensor and/or the shape of the photodiode, among other examples. While increasing the size of the photodiode may increase the full well capacity of the pixel sensor, doing so may come at the expense of decreasing the density of pixel sensors in the pixel sensor array, which may reduce the resolution of the pixel sensor array. To increase the FWC of a pixel sensor, an image sensor device (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor device) may include